P198 / Storage / Connector

U.2 / U.3 SFF-8639 68-position drive connector

U.2/U.3 drive connectors use the SFF-8639 interface family; the cited connector series has 68 positions.

Also called U.2 U.3 SFF-8639 68 pin U.2

A shared drive-edge family does not mean every host, backplane and drive supports the same transport mode.

Look for

Verify U.2 versus U.3 support and the host/backplane protocol path before selecting a cable or drive.

Claim inspection dates: 2026-10-05, 2026-10-13 · Independent review pending

U.2 / U.3 SFF-8639 68-position drive connector: fitted in place. Computer-generated illustration, not a photograph.

U.2 / U.3 SFF-8639 68-position drive connector: original recognition drawing, not to scale.

Image inspection / P198

See the view. Check its scope.

2 registered views for this reference. Different part examples are not automatically mates; all remain not to scale and independently unapproved.

Additional contact regions distinguish the specification interface, not the system protocol. Specification-level device plug; an original source-observed qualitative study, not a pinout or safe-mating guide.

P198 / Source-observed physical study

SFF-TA-8639 / U.2–U.3 context

SFF-TA-8639 revision 2.2 device plug

Two contact-bearing faces of the specification device plug · Other declared component

Not to scale. Technical and rights review pending.

Inspect view & provenance

Editorial checklist separating storage component role, host interface and full system evidence. Not a physical specimen or a compatibility verdict.

P198 / Concept — not physical geometry

Storage: role, interface, system

Editorial evidence checklist; no physical component

Editorial checklist; no component view · Concept only

Not to scale. Technical and rights review pending.

Inspect view & provenance

The useful distinction

Recognize it. Then verify it.

U.2/U.3 drive connectors use the SFF-8639 interface family; the cited connector series has 68 positions. [C198A]

SFF-TA-8639 revision 2.2 defines a 68-contact system, while SFF-9639 explains that a device plug may populate only the contacts required by its use case. [C198B]

The device plug in SFF-TA-8639 Figure 5-1 has contact areas on opposite faces and additional fine-contact regions; one front-facing photograph cannot show the whole interface. [C198C]

SFF-TA-8639 revision 2.2 section 5.2 says its fixed-connector footprint is not generally a replacement for SFF-8482 or SFF-8630 footprints. [C198D]

SFF-9639 revision 2.2 is informational and directs readers to the using-interface standards for definitive signal definitions; it warns that its own tables may become inaccurate. [C198E]

Source-scoped identification facts

Each value retains its exact example, role and measurement axis. Facts from different parts must not be combined into an invented component.

Documented examples; not a mating drawing or compatibility approval
Nominal contacts	68S202Source-backed position count for the cited U.2/U.3 series; not a signal map.
Positions / cavity span	68 (Claim C198A)S202Recorded source-scoped values; named examples do not describe every family variant or establish compatibility. V36 catalogue-expansion identification fact only; not independent technical approval, fabrication data, wiring instruction or end-to-end compatibility proof.
Contact pitch	0.8 mm additional opposite-side contact set described insection5.4S599Named source examples retain separate role, part, view and axis limits; values are not a universal family specification. SFF-8639 Rev2.2 connector interface. Full34-page current official specification is Rev2.2 May6,2024.68positions total, not all necessarily populated. Additional-contact pitch does not replace the separate inheritedSATA/SAS sections.
View convention	Published receptacle and plug views remain distinct; termination-side numbering requires mating-side gender.S599Named source examples retain separate role, part, view and axis limits; values are not a universal family specification. SFF-8639 Rev2.2 connector interface. Full34-page current official specification is Rev2.2 May6,2024.68positions total, not all necessarily populated. Additional-contact pitch does not replace the separate inheritedSATA/SAS sections.

Not recorded: Populated contacts, Contact rows, Dimensions / axis, Connector role, Contact gender / arrangement, Mounting, Coupling / latch, Keying / polarization, Shell / form, Manufacturer, Series, Exact part / implementation, Recorded markings. Unknown fields stay unknown; illustrations supply no measurements or pin assignments.

Recorded variant and source limits

Check the exact device manual before wiring or applying power.
Wilder PCIe Gen-5 U.2 Plug (CLB) test fixture: Table 5 plug identifiers. Names use host direction; this fixture table includes mode-dependent sidebands.
SNIA SFF-TA-1001 U.3 PCIe device plug, single port: Device Plug / PCIe columns, Tables 4-1..4-3. Signal names from host perspective as explicitly stated on p.13.
U.2 / Quad PCIe plug — SNIA reference-guide use: Device plug numbers; PCIe PET/PER names are from the host perspective (Table 5-2 note), even on the device. Physical view follows SFF-8639 device-plug drawing.
U.3 / SFF-TA-1001 universal host receptacle: Use the separate host-receptacle/device-plug columns. PET/PER on a device still use host-perspective naming; E6 and S15 differ between host and device.
U.3 / SFF-TA-1001 PCIe device plug: Use the separate host-receptacle/device-plug columns. PET/PER on a device still use host-perspective naming; E6 and S15 differ between host and device.
Seagate Nytro 5060 2.5-inch U.2 device (named model family): Device manual Table 23 contact numbers. SG1/SG2 are separate ground features and are not counted among the 68 P/S/E contacts.

Report a correction to these facts →

Bounded facts, visible unknowns

Specifications and limits

U.2 / U.3 SFF-8639 68-position drive connector facts and limitations
Documented identification	68-position U.2/U.3 SFF-8639 connector-series form. [C198A]
Source-scoped role and recognition	A common connector is not a common system. Additional contact regions distinguish the specification interface, not the system protocol. [C198B] [C198C] [C198D] [C198E]
Mechanical dimensions	No independently reviewed mechanical drawing in V36; do not use this page for fabrication, fit testing or tolerance work.
Engineering pinout	Source-checked engineering profile available; independent review pending. Open engineering profile →
Verified device list	Not included. Check exact device and accessory documentation.

A boundary, not an omission to guess around.

Use the source-backed form or position count only for identification. Resolve ratings, protocol, direction, wiring, cable construction and exact device support from the relevant equipment and component documentation.

Before you connect

What to check

Identify the exact connector family and variant from the equipment or cable documentation.
Keep shape, contact count, protocol, electrical rating and device support as separate facts.
Do not force, rewire or adapt a connector from this recognition record; resolve the remaining requirements first.

Trace a supported connection class →

Pins & wiring

Pinout

Choose the exact wiring. Pin numbers follow its stated view; a schematic does not establish physical positions. Check your exact device before wiring.

Dark pinout view

What the status labels mean

Confirmed: Recorded research passes agree within this variant; this is not independent human review or hardware validation.
Single source: Only one underlying document, or one pass, supports this assignment.
Device-specific: Supported for the named equipment or wiring only. Check your device’s manual.
Unverified: Missing or conflicting evidence. Do not wire from this row.
Not connected: The source explicitly says NC, no contact or no pin for this wiring.

Wiring variantWilder PCIe Gen-5 U.2 Plug (CLB) test fixture

Wilder PCIe Gen-5 U.2 Plug (CLB) test fixture

Device-specific wiring. Check your device’s manual before connecting or applying power.

View and evidence limits

Table 5 plug identifiers. Names use host direction; this fixture table includes mode-dependent sidebands.

P198 U.2 / U.3 — **Agree** on comparable PCIe lane placement; **partial for sidebands/modes** — Both read **the same SFF-TA-1001 rev 1.1 and SFF-9639 rev 2.2 documents**, with matching hashes. U.3 PCIe-device assignments and the same 11 blank cells agree. U.2 puts lane 0 on E10/E11/E13/E14 and lane 3 on E17/E18/E20/E21; U.3 relocates PCIe lanes to S2-S27. A adds Wilder's U.2 test fixture; B adds Seagate Nytro 5060 and a separate U.3 universal-host column. Host/device E6 and S15, reserved versus fixture-defined HPT roles, and unused power/legacy-data contacts remain variant-specific. Shared SNIA evidence is not independent corroboration; Wilder and Seagate are additional, different device sources.
68 positions. Rev. A printed inside conflicts with Rev_B URL filename; both recorded.
No complete dual-port, SAS or SATA drive variant is asserted. SFF-9639 Rev.2.2 p.7 warns controlling interface standards are definitive. SFF-TA-1001 Rev.1.1 blanks are not reclassified from another use-case column.

Schematic only · physical contact positions unconfirmed. Original drawing · not to scale. Scroll sideways if needed.

Wilder PCIe Gen-5 U.2 Plug (CLB) test fixture — source-scoped contact map
Pin	Signal	What it does	Status
P1	WAKE#	Control, detection or configuration connection; check the source and device.	Device-specific Sources
P2	NC	Not connected or absent in this named wiring.	Not connected Sources
P3	PWRDIS	Control, detection or configuration connection; check the source and device.	Device-specific Sources
P4	IfDet#	Control, detection or configuration connection; check the source and device.	Device-specific Sources
P5	GND	Ground reference and return.	Device-specific Sources
P6	GND	Ground reference and return.	Device-specific Sources
P7	NC	Not connected or absent in this named wiring.	Not connected Sources
P8	NC	Not connected or absent in this named wiring.	Not connected Sources
P9	NC	Not connected or absent in this named wiring.	Not connected Sources
P10	PRSNT#	Control, detection or configuration connection; check the source and device.	Device-specific Sources
P11	ACTIVITY#	Control, detection or configuration connection; check the source and device.	Device-specific Sources
P12	GND	Ground reference and return.	Device-specific Sources
P13	+12 V Precharge	Power connection (+12 V Precharge). Check the specified supply.	Device-specific Sources
P14	+12V	Power connection (+12V). Check the specified supply.	Device-specific Sources
P15	+12V	Power connection (+12V). Check the specified supply.	Device-specific Sources
S1	GND	Ground reference and return.	Device-specific Sources
S2	NC	Not connected or absent in this named wiring.	Not connected Sources
S3	NC	Not connected or absent in this named wiring.	Not connected Sources
S4	GND	Ground reference and return.	Device-specific Sources
S5	NC	Not connected or absent in this named wiring.	Not connected Sources
S6	NC	Not connected or absent in this named wiring.	Not connected Sources
S7	GND	Ground reference and return.	Device-specific Sources
S8	GND	Ground reference and return.	Device-specific Sources
S9	NC	Not connected or absent in this named wiring.	Not connected Sources
S10	NC	Not connected or absent in this named wiring.	Not connected Sources
S11	GND	Ground reference and return.	Device-specific Sources
S12	NC	Not connected or absent in this named wiring.	Not connected Sources
S13	NC	Not connected or absent in this named wiring.	Not connected Sources
S14	GND	Ground reference and return.	Device-specific Sources
S15	HPT0	Control, detection or configuration connection; check the source and device.	Device-specific Sources
S16	GND	Ground reference and return.	Device-specific Sources
S17	PETp1	Signal conductor. Pair, polarity and direction follow this named wiring.	Device-specific Sources
S18	PETn1	Signal conductor. Pair, polarity and direction follow this named wiring.	Device-specific Sources
S19	GND	Ground reference and return.	Device-specific Sources
S20	PERn1	Signal conductor. Pair, polarity and direction follow this named wiring.	Device-specific Sources
S21	PERp1	Signal conductor. Pair, polarity and direction follow this named wiring.	Device-specific Sources
S22	GND	Ground reference and return.	Device-specific Sources
S23	PETp2	Signal conductor. Pair, polarity and direction follow this named wiring.	Device-specific Sources
S24	PETn2	Signal conductor. Pair, polarity and direction follow this named wiring.	Device-specific Sources
S25	GND	Ground reference and return.	Device-specific Sources
S26	PERn2	Signal conductor. Pair, polarity and direction follow this named wiring.	Device-specific Sources
S27	PERp2	Signal conductor. Pair, polarity and direction follow this named wiring.	Device-specific Sources
S28	GND	Ground reference and return.	Device-specific Sources
E1	REFCLKB+	Clock or clock-control connection, as named by this source.	Device-specific Sources
E2	REFCLKB-	Clock or clock-control connection, as named by this source.	Device-specific Sources
E3	+3.3 Vaux	Power connection (+3.3 Vaux). Check the specified supply.	Device-specific Sources
E4	CLKREQ#/PERSTB#	Reset control; check active level and the named device.	Device-specific Sources
E5	PERST#	Reset control; check active level and the named device.	Device-specific Sources
E6	NC	Not connected or absent in this named wiring.	Not connected Sources
E7	REFCLK+	Clock or clock-control connection, as named by this source.	Device-specific Sources
E8	REFCLK-	Clock or clock-control connection, as named by this source.	Device-specific Sources
E9	GND	Ground reference and return.	Device-specific Sources
E10	PETp0	Signal conductor. Pair, polarity and direction follow this named wiring.	Device-specific Sources
E11	PETn0	Signal conductor. Pair, polarity and direction follow this named wiring.	Device-specific Sources
E12	GND	Ground reference and return.	Device-specific Sources
E13	PERn0	Signal conductor. Pair, polarity and direction follow this named wiring.	Device-specific Sources
E14	PERp0	Signal conductor. Pair, polarity and direction follow this named wiring.	Device-specific Sources
E15	GND	Ground reference and return.	Device-specific Sources
E16	HPT1	Control, detection or configuration connection; check the source and device.	Device-specific Sources
E17	PETp3	Signal conductor. Pair, polarity and direction follow this named wiring.	Device-specific Sources
E18	PETn3	Signal conductor. Pair, polarity and direction follow this named wiring.	Device-specific Sources
E19	GND	Ground reference and return.	Device-specific Sources
E20	PERn3	Signal conductor. Pair, polarity and direction follow this named wiring.	Device-specific Sources
E21	PERp3	Signal conductor. Pair, polarity and direction follow this named wiring.	Device-specific Sources
E22	GND	Ground reference and return.	Device-specific Sources
E23	SMBCLK	Clock or clock-control connection, as named by this source.	Device-specific Sources
E24	SMBDAT	Control, detection or configuration connection; check the source and device.	Device-specific Sources
E25	DUALPORTEN#	Control, detection or configuration connection; check the source and device.	Device-specific Sources

Sources (2)

S774 · Wilder Technologies, LLC · PCIe Gen-5 U.2 Test Adapters User Manual
910-0078-000 Rev. A on cover and p.29; URL filename says Rev_B / 10-31-2024 · p.29, Table 5 PCIe Gen-5 U.2 Plug (CLB) Pin Assignments, all grouped and individual rows
S775 · SNIA SFF TWG · SFF-9639: Reference Guide for Multifunction 6X Unshielded Connector Pinouts
Rev 2.2, May 2, 2025 | Rev. 2.2, May 2, 2025 · p.8, Table 5-2 PCIe naming note: receiver on device has transmitter signal name

SNIA SFF-TA-1001 U.3 PCIe device plug, single port

View and evidence limits

Device Plug / PCIe columns, Tables 4-1..4-3. Signal names from host perspective as explicitly stated on p.13.

P198 U.2 / U.3 — **Agree** on comparable PCIe lane placement; **partial for sidebands/modes** — Both read **the same SFF-TA-1001 rev 1.1 and SFF-9639 rev 2.2 documents**, with matching hashes. U.3 PCIe-device assignments and the same 11 blank cells agree. U.2 puts lane 0 on E10/E11/E13/E14 and lane 3 on E17/E18/E20/E21; U.3 relocates PCIe lanes to S2-S27. A adds Wilder's U.2 test fixture; B adds Seagate Nytro 5060 and a separate U.3 universal-host column. Host/device E6 and S15, reserved versus fixture-defined HPT roles, and unused power/legacy-data contacts remain variant-specific. Shared SNIA evidence is not independent corroboration; Wilder and Seagate are additional, different device sources.
68 positions. P7-P9 and E10/E11/E13/E14/E17/E18/E20/E21 have blank device/PCIe cells; remain unverified.
No complete dual-port, SAS or SATA drive variant is asserted. SFF-9639 Rev.2.2 p.7 warns controlling interface standards are definitive. SFF-TA-1001 Rev.1.1 blanks are not reclassified from another use-case column.

Schematic only · physical contact positions unconfirmed. Original drawing · not to scale. Scroll sideways if needed.

SNIA SFF-TA-1001 U.3 PCIe device plug, single port — source-scoped contact map
Pin	Signal	What it does	Status
P1	WAKE#	Control, detection or configuration connection; check the source and device.	Single source Sources
P2	Reserved	Reserved; no general-purpose wiring is established.	Single source Sources
P3	PWRDIS	Control, detection or configuration connection; check the source and device.	Single source Sources
P4	IfDet#	Control, detection or configuration connection; check the source and device.	Single source Sources
P5	Ground	Ground reference and return.	Single source Sources
P6	Ground	Ground reference and return.	Single source Sources
P7	Not confirmed	No settled assignment. Do not wire from this row.	Unverified Sources
P8	Not confirmed	No settled assignment. Do not wire from this row.	Unverified Sources
P9	Not confirmed	No settled assignment. Do not wire from this row.	Unverified Sources
P10	PRSNT#	Control, detection or configuration connection; check the source and device.	Single source Sources
P11	ACTIVITY#	Control, detection or configuration connection; check the source and device.	Single source Sources
P12	Ground	Ground reference and return.	Single source Sources
P13	+12 V Precharge	Power connection (+12 V Precharge). Check the specified supply.	Single source Sources
P14	+12 V	Power connection (+12 V). Check the specified supply.	Single source Sources
P15	+12 V	Power connection (+12 V). Check the specified supply.	Single source Sources
S1	Ground	Ground reference and return.	Single source Sources
S2	PETp0	Signal conductor. Pair, polarity and direction follow this named wiring.	Single source Sources
S3	PETn0	Signal conductor. Pair, polarity and direction follow this named wiring.	Single source Sources
S4	Ground	Ground reference and return.	Single source Sources
S5	PERn0	Signal conductor. Pair, polarity and direction follow this named wiring.	Single source Sources
S6	PERp0	Signal conductor. Pair, polarity and direction follow this named wiring.	Single source Sources
S7	Ground	Ground reference and return.	Single source Sources
S8	Ground	Ground reference and return.	Single source Sources
S9	PETp1	Signal conductor. Pair, polarity and direction follow this named wiring.	Single source Sources
S10	PETn1	Signal conductor. Pair, polarity and direction follow this named wiring.	Single source Sources
S11	Ground	Ground reference and return.	Single source Sources
S12	PERn1	Signal conductor. Pair, polarity and direction follow this named wiring.	Single source Sources
S13	PERp1	Signal conductor. Pair, polarity and direction follow this named wiring.	Single source Sources
S14	Ground	Ground reference and return.	Single source Sources
S15	HPT0	Control, detection or configuration connection; check the source and device.	Single source Sources
S16	Ground	Ground reference and return.	Single source Sources
S17	PETp2	Signal conductor. Pair, polarity and direction follow this named wiring.	Single source Sources
S18	PETn2	Signal conductor. Pair, polarity and direction follow this named wiring.	Single source Sources
S19	Ground	Ground reference and return.	Single source Sources
S20	PERn2	Signal conductor. Pair, polarity and direction follow this named wiring.	Single source Sources
S21	PERp2	Signal conductor. Pair, polarity and direction follow this named wiring.	Single source Sources
S22	Ground	Ground reference and return.	Single source Sources
S23	PETp3	Signal conductor. Pair, polarity and direction follow this named wiring.	Single source Sources
S24	PETn3	Signal conductor. Pair, polarity and direction follow this named wiring.	Single source Sources
S25	Ground	Ground reference and return.	Single source Sources
S26	PERn3	Signal conductor. Pair, polarity and direction follow this named wiring.	Single source Sources
S27	PERp3	Signal conductor. Pair, polarity and direction follow this named wiring.	Single source Sources
S28	Ground	Ground reference and return.	Single source Sources
E1	REFCLKB+	Clock or clock-control connection, as named by this source.	Single source Sources
E2	REFCLKB-	Clock or clock-control connection, as named by this source.	Single source Sources
E3	+3.3 Vaux	Power connection (+3.3 Vaux). Check the specified supply.	Single source Sources
E4	PERSTB#	Reset control; check active level and the named device.	Single source Sources
E5	PERST#	Reset control; check active level and the named device.	Single source Sources
E6	Ground	Ground reference and return.	Single source Sources
E7	REFCLK+	Clock or clock-control connection, as named by this source.	Single source Sources
E8	REFCLK-	Clock or clock-control connection, as named by this source.	Single source Sources
E9	Ground	Ground reference and return.	Single source Sources
E10	Not confirmed	No settled assignment. Do not wire from this row.	Unverified Sources
E11	Not confirmed	No settled assignment. Do not wire from this row.	Unverified Sources
E12	Ground	Ground reference and return.	Single source Sources
E13	Not confirmed	No settled assignment. Do not wire from this row.	Unverified Sources
E14	Not confirmed	No settled assignment. Do not wire from this row.	Unverified Sources
E15	Ground	Ground reference and return.	Single source Sources
E16	HPT1	Control, detection or configuration connection; check the source and device.	Single source Sources
E17	Not confirmed	No settled assignment. Do not wire from this row.	Unverified Sources
E18	Not confirmed	No settled assignment. Do not wire from this row.	Unverified Sources
E19	Ground	Ground reference and return.	Single source Sources
E20	Not confirmed	No settled assignment. Do not wire from this row.	Unverified Sources
E21	Not confirmed	No settled assignment. Do not wire from this row.	Unverified Sources
E22	Ground	Ground reference and return.	Single source Sources
E23	SMBCLK	Clock or clock-control connection, as named by this source.	Single source Sources
E24	SMBDAT	Control, detection or configuration connection; check the source and device.	Single source Sources
E25	DualPortEn#	Control, detection or configuration connection; check the source and device.	Single source Sources

Sources (1)

S776 · SNIA SFF TA TWG · SFF-TA-1001: Universal x4 Link Definition for SFF-8639
Rev 1.1, May 28, 2018 | Rev. 1.1, May 28, 2018 · pp.12-13 Tables 4-1 P Series, 4-2 S Series, 4-3 E Series; p.16 Table 4-7 single-port routing; p.13 PET/PER direction notes

U.2 / Quad PCIe plug — SNIA reference-guide use

View and evidence limits

Device plug numbers; PCIe PET/PER names are from the host perspective (Table 5-2 note), even on the device. Physical view follows SFF-8639 device-plug drawing.

P198 U.2 / U.3 — **Agree** on comparable PCIe lane placement; **partial for sidebands/modes** — Both read **the same SFF-TA-1001 rev 1.1 and SFF-9639 rev 2.2 documents**, with matching hashes. U.3 PCIe-device assignments and the same 11 blank cells agree. U.2 puts lane 0 on E10/E11/E13/E14 and lane 3 on E17/E18/E20/E21; U.3 relocates PCIe lanes to S2-S27. A adds Wilder's U.2 test fixture; B adds Seagate Nytro 5060 and a separate U.3 universal-host column. Host/device E6 and S15, reserved versus fixture-defined HPT roles, and unused power/legacy-data contacts remain variant-specific. Shared SNIA evidence is not independent corroboration; Wilder and Seagate are additional, different device sources.
Reference-guide map, not a replacement for the PCI-SIG using specification. Blank use-case cells remain unverified.
SFF-9639 expressly warns in section 5 that its tables are a reference guide and the using-interface specifications are definitive. Blank cells were not converted to NC/reserved. The PCI-SIG U.2 module specification was not obtained in this pass.
Only the explicit SFF-TA-1001 host/PCIe device columns and single-x4 numbering are mapped. SAS/SATA protocol-specific uses, dual-x2 remaps, Gen-Z and NVMe-oF are not silently combined into those variants; Tables 4-4/4-7 and SFF-9639 Table 6-1 must be followed for the selected mode.

Schematic only · physical contact positions unconfirmed. Original drawing · not to scale. Scroll sideways if needed.

U.2 / Quad PCIe plug — SNIA reference-guide use — source-scoped contact map
Pin	Signal	What it does	Status
P1	WAKE#	Control, detection or configuration connection; check the source and device.	Single source Sources
P2	Not confirmed	No settled assignment. Do not wire from this row.	Unverified Sources
P3	PWRDIS	Control, detection or configuration connection; check the source and device.	Single source Sources
P4	IfDet#	Control, detection or configuration connection; check the source and device.	Single source Sources
P5	Ground	Ground reference and return.	Single source Sources
P6	Ground	Ground reference and return.	Single source Sources
P7	Not confirmed	No settled assignment. Do not wire from this row.	Unverified Sources
P8	Not confirmed	No settled assignment. Do not wire from this row.	Unverified Sources
P9	Not confirmed	No settled assignment. Do not wire from this row.	Unverified Sources
P10	PRSNT#	Control, detection or configuration connection; check the source and device.	Single source Sources
P11	ACTIVITY#	Control, detection or configuration connection; check the source and device.	Single source Sources
P12	Ground	Ground reference and return.	Single source Sources
P13	+12V Precharge	Power connection (+12V Precharge). Check the specified supply.	Single source Sources
P14	+12V	Power connection (+12V). Check the specified supply.	Single source Sources
P15	+12V	Power connection (+12V). Check the specified supply.	Single source Sources
S1	Ground	Ground reference and return.	Single source Sources
S2	Not confirmed	No settled assignment. Do not wire from this row.	Unverified Sources
S3	Not confirmed	No settled assignment. Do not wire from this row.	Unverified Sources
S4	Ground	Ground reference and return.	Single source Sources
S5	Not confirmed	No settled assignment. Do not wire from this row.	Unverified Sources
S6	Not confirmed	No settled assignment. Do not wire from this row.	Unverified Sources
S7	Ground	Ground reference and return.	Single source Sources
S8	Ground	Ground reference and return.	Single source Sources
S9	Not confirmed	No settled assignment. Do not wire from this row.	Unverified Sources
S10	Not confirmed	No settled assignment. Do not wire from this row.	Unverified Sources
S11	Ground	Ground reference and return.	Single source Sources
S12	Not confirmed	No settled assignment. Do not wire from this row.	Unverified Sources
S13	Not confirmed	No settled assignment. Do not wire from this row.	Unverified Sources
S14	Ground	Ground reference and return.	Single source Sources
S15	Reserved	Reserved; no general-purpose wiring is established.	Single source Sources
S16	Ground	Ground reference and return.	Single source Sources
S17	PETp1	Signal conductor. Pair, polarity and direction follow this named wiring.	Single source Sources
S18	PETn1	Signal conductor. Pair, polarity and direction follow this named wiring.	Single source Sources
S19	Ground	Ground reference and return.	Single source Sources
S20	PERn1	Signal conductor. Pair, polarity and direction follow this named wiring.	Single source Sources
S21	PERp1	Signal conductor. Pair, polarity and direction follow this named wiring.	Single source Sources
S22	Ground	Ground reference and return.	Single source Sources
S23	PETp2	Signal conductor. Pair, polarity and direction follow this named wiring.	Single source Sources
S24	PETn2	Signal conductor. Pair, polarity and direction follow this named wiring.	Single source Sources
S25	Ground	Ground reference and return.	Single source Sources
S26	PERn2	Signal conductor. Pair, polarity and direction follow this named wiring.	Single source Sources
S27	PERp2	Signal conductor. Pair, polarity and direction follow this named wiring.	Single source Sources
S28	Ground	Ground reference and return.	Single source Sources
E1	REFCLKB+	Clock or clock-control connection, as named by this source.	Single source Sources
E2	REFCLKB-	Clock or clock-control connection, as named by this source.	Single source Sources
E3	+3.3Vaux	Power connection (+3.3Vaux). Check the specified supply.	Single source Sources
E4	CLKREQ#/PERSTB#	Reset control; check active level and the named device.	Single source Sources
E5	PERST#	Reset control; check active level and the named device.	Single source Sources
E6	Reserved	Reserved; no general-purpose wiring is established.	Single source Sources
E7	REFCLK+	Clock or clock-control connection, as named by this source.	Single source Sources
E8	REFCLK-	Clock or clock-control connection, as named by this source.	Single source Sources
E9	Ground	Ground reference and return.	Single source Sources
E10	PETp0	Signal conductor. Pair, polarity and direction follow this named wiring.	Single source Sources
E11	PETn0	Signal conductor. Pair, polarity and direction follow this named wiring.	Single source Sources
E12	Ground	Ground reference and return.	Single source Sources
E13	PERn0	Signal conductor. Pair, polarity and direction follow this named wiring.	Single source Sources
E14	PERp0	Signal conductor. Pair, polarity and direction follow this named wiring.	Single source Sources
E15	Ground	Ground reference and return.	Single source Sources
E16	Reserved	Reserved; no general-purpose wiring is established.	Single source Sources
E17	PETp3	Signal conductor. Pair, polarity and direction follow this named wiring.	Single source Sources
E18	PETn3	Signal conductor. Pair, polarity and direction follow this named wiring.	Single source Sources
E19	Ground	Ground reference and return.	Single source Sources
E20	PERn3	Signal conductor. Pair, polarity and direction follow this named wiring.	Single source Sources
E21	PERp3	Signal conductor. Pair, polarity and direction follow this named wiring.	Single source Sources
E22	Ground	Ground reference and return.	Single source Sources
E23	SMBCLK	Clock or clock-control connection, as named by this source.	Single source Sources
E24	SMBDAT	Control, detection or configuration connection; check the source and device.	Single source Sources
E25	DualPortEn#	Control, detection or configuration connection; check the source and device.	Single source Sources

Sources (2)

S775 · SNIA SFF TWG · SFF-9639: Reference Guide for Multifunction 6X Unshielded Connector Pinouts
Rev 2.2, May 2, 2025 | Rev. 2.2, May 2, 2025 · p. 7, Table 5-1 P Series Signals (Plug), Quad PCIe column, row P1; p. 7 section 5 reference-guide warning; p. 7, Table 5-1 P Series Signals (Plug), Quad PCIe column, row P2; p. 7 section 5 reference-guide warning; p. 7, Table 5-1 P Series Signals (Plug), Quad PCIe column, row P3; p. 7 section 5 reference-guide warning; p. 7, Table 5-1 P Series Signals (Plug), Quad PCIe column, row P4; p. 7 section 5 reference-guide warning; p. 7, Table 5-1 P Series Signals (Plug), Quad PCIe column, row P5; p. 7 section 5 reference-guide warning; p. 7, Table 5-1 P Series Signals (Plug), Quad PCIe column, row P6; p. 7 section 5 reference-guide warning; p. 7, Table 5-1 P Series Signals (Plug), Quad PCIe column, row P7; p. 7 section 5 reference-guide warning; p. 7, Table 5-1 P Series Signals (Plug), Quad PCIe column, row P8; p. 7 section 5 reference-guide warning; p. 7, Table 5-1 P Series Signals (Plug), Quad PCIe column, row P9; p. 7 section 5 reference-guide warning; p. 7, Table 5-1 P Series Signals (Plug), Quad PCIe column, row P10; p. 7 section 5 reference-guide warning; p. 7, Table 5-1 P Series Signals (Plug), Quad PCIe column, row P11; p. 7 section 5 reference-guide warning; p. 7, Table 5-1 P Series Signals (Plug), Quad PCIe column, row P12; p. 7 section 5 reference-guide warning; p. 7, Table 5-1 P Series Signals (Plug), Quad PCIe column, row P13; p. 7 section 5 reference-guide warning; p. 7, Table 5-1 P Series Signals (Plug), Quad PCIe column, row P14; p. 7 section 5 reference-guide warning; p. 7, Table 5-1 P Series Signals (Plug), Quad PCIe column, row P15; p. 7 section 5 reference-guide warning; p. 8, Table 5-2 S Series Signals (Plug), Quad PCIe column, row S1; p. 7 section 5 reference-guide warning; p. 8, Table 5-2 S Series Signals (Plug), Quad PCIe column, row S2; p. 7 section 5 reference-guide warning; p. 8, Table 5-2 S Series Signals (Plug), Quad PCIe column, row S3; p. 7 section 5 reference-guide warning; p. 8, Table 5-2 S Series Signals (Plug), Quad PCIe column, row S4; p. 7 section 5 reference-guide warning; p. 8, Table 5-2 S Series Signals (Plug), Quad PCIe column, row S5; p. 7 section 5 reference-guide warning; p. 8, Table 5-2 S Series Signals (Plug), Quad PCIe column, row S6; p. 7 section 5 reference-guide warning; p. 8, Table 5-2 S Series Signals (Plug), Quad PCIe column, row S7; p. 7 section 5 reference-guide warning; p. 8, Table 5-2 S Series Signals (Plug), Quad PCIe column, row S8; p. 7 section 5 reference-guide warning; p. 8, Table 5-2 S Series Signals (Plug), Quad PCIe column, row S9; p. 7 section 5 reference-guide warning; p. 8, Table 5-2 S Series Signals (Plug), Quad PCIe column, row S10; p. 7 section 5 reference-guide warning; p. 8, Table 5-2 S Series Signals (Plug), Quad PCIe column, row S11; p. 7 section 5 reference-guide warning; p. 8, Table 5-2 S Series Signals (Plug), Quad PCIe column, row S12; p. 7 section 5 reference-guide warning; p. 8, Table 5-2 S Series Signals (Plug), Quad PCIe column, row S13; p. 7 section 5 reference-guide warning; p. 8, Table 5-2 S Series Signals (Plug), Quad PCIe column, row S14; p. 7 section 5 reference-guide warning; p. 8, Table 5-2 S Series Signals (Plug), Quad PCIe column, row S15; p. 7 section 5 reference-guide warning; p. 8, Table 5-2 S Series Signals (Plug), Quad PCIe column, row S16; p. 7 section 5 reference-guide warning; p. 8, Table 5-2 S Series Signals (Plug), Quad PCIe column, row S17; p. 7 section 5 reference-guide warning; p. 8, Table 5-2 S Series Signals (Plug), Quad PCIe column, row S18; p. 7 section 5 reference-guide warning; p. 8, Table 5-2 S Series Signals (Plug), Quad PCIe column, row S19; p. 7 section 5 reference-guide warning; p. 8, Table 5-2 S Series Signals (Plug), Quad PCIe column, row S20; p. 7 section 5 reference-guide warning; p. 8, Table 5-2 S Series Signals (Plug), Quad PCIe column, row S21; p. 7 section 5 reference-guide warning; p. 8, Table 5-2 S Series Signals (Plug), Quad PCIe column, row S22; p. 7 section 5 reference-guide warning; p. 8, Table 5-2 S Series Signals (Plug), Quad PCIe column, row S23; p. 7 section 5 reference-guide warning; p. 8, Table 5-2 S Series Signals (Plug), Quad PCIe column, row S24; p. 7 section 5 reference-guide warning; p. 8, Table 5-2 S Series Signals (Plug), Quad PCIe column, row S25; p. 7 section 5 reference-guide warning; p. 8, Table 5-2 S Series Signals (Plug), Quad PCIe column, row S26; p. 7 section 5 reference-guide warning; p. 8, Table 5-2 S Series Signals (Plug), Quad PCIe column, row S27; p. 7 section 5 reference-guide warning; p. 8, Table 5-2 S Series Signals (Plug), Quad PCIe column, row S28; p. 7 section 5 reference-guide warning; p. 9, Table 5-3 E Series Signals (Plug), Quad PCIe column, row E1; p. 7 section 5 reference-guide warning; p. 9, Table 5-3 E Series Signals (Plug), Quad PCIe column, row E2; p. 7 section 5 reference-guide warning; p. 9, Table 5-3 E Series Signals (Plug), Quad PCIe column, row E3; p. 7 section 5 reference-guide warning; p. 9, Table 5-3 E Series Signals (Plug), Quad PCIe column, row E4; p. 7 section 5 reference-guide warning; p. 9, Table 5-3 E Series Signals (Plug), Quad PCIe column, row E5; p. 7 section 5 reference-guide warning; p. 9, Table 5-3 E Series Signals (Plug), Quad PCIe column, row E6; p. 7 section 5 reference-guide warning; p. 9, Table 5-3 E Series Signals (Plug), Quad PCIe column, row E7; p. 7 section 5 reference-guide warning; p. 9, Table 5-3 E Series Signals (Plug), Quad PCIe column, row E8; p. 7 section 5 reference-guide warning; p. 9, Table 5-3 E Series Signals (Plug), Quad PCIe column, row E9; p. 7 section 5 reference-guide warning; p. 9, Table 5-3 E Series Signals (Plug), Quad PCIe column, row E10; p. 7 section 5 reference-guide warning; p. 9, Table 5-3 E Series Signals (Plug), Quad PCIe column, row E11; p. 7 section 5 reference-guide warning; p. 9, Table 5-3 E Series Signals (Plug), Quad PCIe column, row E12; p. 7 section 5 reference-guide warning; p. 9, Table 5-3 E Series Signals (Plug), Quad PCIe column, row E13; p. 7 section 5 reference-guide warning; p. 9, Table 5-3 E Series Signals (Plug), Quad PCIe column, row E14; p. 7 section 5 reference-guide warning; p. 9, Table 5-3 E Series Signals (Plug), Quad PCIe column, row E15; p. 7 section 5 reference-guide warning; p. 9, Table 5-3 E Series Signals (Plug), Quad PCIe column, row E16; p. 7 section 5 reference-guide warning; p. 9, Table 5-3 E Series Signals (Plug), Quad PCIe column, row E17; p. 7 section 5 reference-guide warning; p. 9, Table 5-3 E Series Signals (Plug), Quad PCIe column, row E18; p. 7 section 5 reference-guide warning; p. 9, Table 5-3 E Series Signals (Plug), Quad PCIe column, row E19; p. 7 section 5 reference-guide warning; p. 9, Table 5-3 E Series Signals (Plug), Quad PCIe column, row E20; p. 7 section 5 reference-guide warning; p. 9, Table 5-3 E Series Signals (Plug), Quad PCIe column, row E21; p. 7 section 5 reference-guide warning; p. 9, Table 5-3 E Series Signals (Plug), Quad PCIe column, row E22; p. 7 section 5 reference-guide warning; p. 9, Table 5-3 E Series Signals (Plug), Quad PCIe column, row E23; p. 7 section 5 reference-guide warning; p. 9, Table 5-3 E Series Signals (Plug), Quad PCIe column, row E24; p. 7 section 5 reference-guide warning; p. 9, Table 5-3 E Series Signals (Plug), Quad PCIe column, row E25; p. 7 section 5 reference-guide warning
S777 · SNIA SFF TA TWG · SFF-8639: Multifunction 6X Unshielded Connector
Rev 2.2, May 6, 2024 · p. 22 section 6.1 and Figure 6-1 Contact Numbering Scheme; p. 15 Figure 5-1 Device Free (Plug) Connector

U.3 / SFF-TA-1001 universal host receptacle

View and evidence limits

Use the separate host-receptacle/device-plug columns. PET/PER on a device still use host-perspective naming; E6 and S15 differ between host and device.

P198 U.2 / U.3 — **Agree** on comparable PCIe lane placement; **partial for sidebands/modes** — Both read **the same SFF-TA-1001 rev 1.1 and SFF-9639 rev 2.2 documents**, with matching hashes. U.3 PCIe-device assignments and the same 11 blank cells agree. U.2 puts lane 0 on E10/E11/E13/E14 and lane 3 on E17/E18/E20/E21; U.3 relocates PCIe lanes to S2-S27. A adds Wilder's U.2 test fixture; B adds Seagate Nytro 5060 and a separate U.3 universal-host column. Host/device E6 and S15, reserved versus fixture-defined HPT roles, and unused power/legacy-data contacts remain variant-specific. Shared SNIA evidence is not independent corroboration; Wilder and Seagate are additional, different device sources.
Single x4 PCIe lane numbers shown; dual-port use redistributes lane numbering. Blank source cells remain unverified.
SFF-9639 expressly warns in section 5 that its tables are a reference guide and the using-interface specifications are definitive. Blank cells were not converted to NC/reserved. The PCI-SIG U.2 module specification was not obtained in this pass.
Only the explicit SFF-TA-1001 host/PCIe device columns and single-x4 numbering are mapped. SAS/SATA protocol-specific uses, dual-x2 remaps, Gen-Z and NVMe-oF are not silently combined into those variants; Tables 4-4/4-7 and SFF-9639 Table 6-1 must be followed for the selected mode.

Schematic only · physical contact positions unconfirmed. Original drawing · not to scale. Scroll sideways if needed.

U.3 / SFF-TA-1001 universal host receptacle — source-scoped contact map
Pin	Signal	What it does	Status
P1	WAKE#	Control, detection or configuration connection; check the source and device.	Single source Sources
P2	Not confirmed	No settled assignment. Do not wire from this row.	Unverified Sources
P3	PWRDIS	Control, detection or configuration connection; check the source and device.	Single source Sources
P4	IfDet#	Control, detection or configuration connection; check the source and device.	Single source Sources
P5	Ground	Ground reference and return.	Single source Sources
P6	Ground	Ground reference and return.	Single source Sources
P7	+5V	Power connection (+5V). Check the specified supply.	Single source Sources
P8	+5V	Power connection (+5V). Check the specified supply.	Single source Sources
P9	+5V	Power connection (+5V). Check the specified supply.	Single source Sources
P10	PRSNT#	Control, detection or configuration connection; check the source and device.	Single source Sources
P11	ACTIVITY LED	Control, detection or configuration connection; check the source and device.	Single source Sources
P12	Ground	Ground reference and return.	Single source Sources
P13	+12V	Power connection (+12V). Check the specified supply.	Single source Sources
P14	+12V	Power connection (+12V). Check the specified supply.	Single source Sources
P15	+12V	Power connection (+12V). Check the specified supply.	Single source Sources
S1	Ground	Ground reference and return.	Single source Sources
S2	TX p0	Signal conductor. Pair, polarity and direction follow this named wiring.	Single source Sources
S3	TX n0	Signal conductor. Pair, polarity and direction follow this named wiring.	Single source Sources
S4	Ground	Ground reference and return.	Single source Sources
S5	RX n0	Signal conductor. Pair, polarity and direction follow this named wiring.	Single source Sources
S6	RX p0	Signal conductor. Pair, polarity and direction follow this named wiring.	Single source Sources
S7	Ground	Ground reference and return.	Single source Sources
S8	Ground	Ground reference and return.	Single source Sources
S9	TX p1	Signal conductor. Pair, polarity and direction follow this named wiring.	Single source Sources
S10	TX n1	Signal conductor. Pair, polarity and direction follow this named wiring.	Single source Sources
S11	Ground	Ground reference and return.	Single source Sources
S12	RX n1	Signal conductor. Pair, polarity and direction follow this named wiring.	Single source Sources
S13	RX p1	Signal conductor. Pair, polarity and direction follow this named wiring.	Single source Sources
S14	Ground	Ground reference and return.	Single source Sources
S15	Ground	Ground reference and return.	Single source Sources
S16	Ground	Ground reference and return.	Single source Sources
S17	TX p2	Signal conductor. Pair, polarity and direction follow this named wiring.	Single source Sources
S18	TX n2	Signal conductor. Pair, polarity and direction follow this named wiring.	Single source Sources
S19	Ground	Ground reference and return.	Single source Sources
S20	RX n2	Signal conductor. Pair, polarity and direction follow this named wiring.	Single source Sources
S21	RX p2	Signal conductor. Pair, polarity and direction follow this named wiring.	Single source Sources
S22	Ground	Ground reference and return.	Single source Sources
S23	TX p3	Signal conductor. Pair, polarity and direction follow this named wiring.	Single source Sources
S24	TX n3	Signal conductor. Pair, polarity and direction follow this named wiring.	Single source Sources
S25	Ground	Ground reference and return.	Single source Sources
S26	RX n3	Signal conductor. Pair, polarity and direction follow this named wiring.	Single source Sources
S27	RX p3	Signal conductor. Pair, polarity and direction follow this named wiring.	Single source Sources
S28	Ground	Ground reference and return.	Single source Sources
E1	REFCLKB+	Clock or clock-control connection, as named by this source.	Single source Sources
E2	REFCLKB-	Clock or clock-control connection, as named by this source.	Single source Sources
E3	+3.3Vaux	Power connection (+3.3Vaux). Check the specified supply.	Single source Sources
E4	PERSTB#	Reset control; check active level and the named device.	Single source Sources
E5	PERST#	Reset control; check active level and the named device.	Single source Sources
E6	IfDet2#	Control, detection or configuration connection; check the source and device.	Single source Sources
E7	REFCLK+	Clock or clock-control connection, as named by this source.	Single source Sources
E8	REFCLK-	Clock or clock-control connection, as named by this source.	Single source Sources
E9	Ground	Ground reference and return.	Single source Sources
E10	Not confirmed	No settled assignment. Do not wire from this row.	Unverified Sources
E11	Not confirmed	No settled assignment. Do not wire from this row.	Unverified Sources
E12	Ground	Ground reference and return.	Single source Sources
E13	Not confirmed	No settled assignment. Do not wire from this row.	Unverified Sources
E14	Not confirmed	No settled assignment. Do not wire from this row.	Unverified Sources
E15	Ground	Ground reference and return.	Single source Sources
E16	HPT1	Control, detection or configuration connection; check the source and device.	Single source Sources
E17	Not confirmed	No settled assignment. Do not wire from this row.	Unverified Sources
E18	Not confirmed	No settled assignment. Do not wire from this row.	Unverified Sources
E19	Ground	Ground reference and return.	Single source Sources
E20	Not confirmed	No settled assignment. Do not wire from this row.	Unverified Sources
E21	Not confirmed	No settled assignment. Do not wire from this row.	Unverified Sources
E22	Ground	Ground reference and return.	Single source Sources
E23	SMBCLK	Clock or clock-control connection, as named by this source.	Single source Sources
E24	SMBDAT	Control, detection or configuration connection; check the source and device.	Single source Sources
E25	DualPortEn#	Control, detection or configuration connection; check the source and device.	Single source Sources

Sources (2)

S776 · SNIA SFF TA TWG · SFF-TA-1001: Universal x4 Link Definition for SFF-8639
Rev 1.1, May 28, 2018 | Rev. 1.1, May 28, 2018 · p. 12, Table 4-1 P Series Signals, Host receptacle column, row P1; pp. 14-16 port/detection definitions; p. 12, Table 4-1 P Series Signals, Host receptacle column, row P2; pp. 14-16 port/detection definitions; p. 12, Table 4-1 P Series Signals, Host receptacle column, row P3; pp. 14-16 port/detection definitions; p. 12, Table 4-1 P Series Signals, Host receptacle column, row P4; pp. 14-16 port/detection definitions; p. 12, Table 4-1 P Series Signals, Host receptacle column, row P5; pp. 14-16 port/detection definitions; p. 12, Table 4-1 P Series Signals, Host receptacle column, row P6; pp. 14-16 port/detection definitions; p. 12, Table 4-1 P Series Signals, Host receptacle column, row P7; pp. 14-16 port/detection definitions; p. 12, Table 4-1 P Series Signals, Host receptacle column, row P8; pp. 14-16 port/detection definitions; p. 12, Table 4-1 P Series Signals, Host receptacle column, row P9; pp. 14-16 port/detection definitions; p. 12, Table 4-1 P Series Signals, Host receptacle column, row P10; pp. 14-16 port/detection definitions; p. 12, Table 4-1 P Series Signals, Host receptacle column, row P11; pp. 14-16 port/detection definitions; p. 12, Table 4-1 P Series Signals, Host receptacle column, row P12; pp. 14-16 port/detection definitions; p. 12, Table 4-1 P Series Signals, Host receptacle column, row P13; pp. 14-16 port/detection definitions; p. 12, Table 4-1 P Series Signals, Host receptacle column, row P14; pp. 14-16 port/detection definitions; p. 12, Table 4-1 P Series Signals, Host receptacle column, row P15; pp. 14-16 port/detection definitions; p. 12, Table 4-2 S Series Signals, Host receptacle column, row S1; pp. 14-16 port/detection definitions; p. 12, Table 4-2 S Series Signals, Host receptacle column, row S2; pp. 14-16 port/detection definitions; p. 12, Table 4-2 S Series Signals, Host receptacle column, row S3; pp. 14-16 port/detection definitions; p. 12, Table 4-2 S Series Signals, Host receptacle column, row S4; pp. 14-16 port/detection definitions; p. 12, Table 4-2 S Series Signals, Host receptacle column, row S5; pp. 14-16 port/detection definitions; p. 12, Table 4-2 S Series Signals, Host receptacle column, row S6; pp. 14-16 port/detection definitions; p. 12, Table 4-2 S Series Signals, Host receptacle column, row S7; pp. 14-16 port/detection definitions; p. 12, Table 4-2 S Series Signals, Host receptacle column, row S8; pp. 14-16 port/detection definitions; p. 12, Table 4-2 S Series Signals, Host receptacle column, row S9; pp. 14-16 port/detection definitions; p. 12, Table 4-2 S Series Signals, Host receptacle column, row S10; pp. 14-16 port/detection definitions; p. 12, Table 4-2 S Series Signals, Host receptacle column, row S11; pp. 14-16 port/detection definitions; p. 12, Table 4-2 S Series Signals, Host receptacle column, row S12; pp. 14-16 port/detection definitions; p. 12, Table 4-2 S Series Signals, Host receptacle column, row S13; pp. 14-16 port/detection definitions; p. 12, Table 4-2 S Series Signals, Host receptacle column, row S14; pp. 14-16 port/detection definitions; p. 12, Table 4-2 S Series Signals, Host receptacle column, row S15; pp. 14-16 port/detection definitions; p. 12, Table 4-2 S Series Signals, Host receptacle column, row S16; pp. 14-16 port/detection definitions; p. 12, Table 4-2 S Series Signals, Host receptacle column, row S17; pp. 14-16 port/detection definitions; p. 12, Table 4-2 S Series Signals, Host receptacle column, row S18; pp. 14-16 port/detection definitions; p. 12, Table 4-2 S Series Signals, Host receptacle column, row S19; pp. 14-16 port/detection definitions; p. 12, Table 4-2 S Series Signals, Host receptacle column, row S20; pp. 14-16 port/detection definitions; p. 12, Table 4-2 S Series Signals, Host receptacle column, row S21; pp. 14-16 port/detection definitions; p. 12, Table 4-2 S Series Signals, Host receptacle column, row S22; pp. 14-16 port/detection definitions; p. 12, Table 4-2 S Series Signals, Host receptacle column, row S23; pp. 14-16 port/detection definitions; p. 12, Table 4-2 S Series Signals, Host receptacle column, row S24; pp. 14-16 port/detection definitions; p. 12, Table 4-2 S Series Signals, Host receptacle column, row S25; pp. 14-16 port/detection definitions; p. 12, Table 4-2 S Series Signals, Host receptacle column, row S26; pp. 14-16 port/detection definitions; p. 12, Table 4-2 S Series Signals, Host receptacle column, row S27; pp. 14-16 port/detection definitions; p. 12, Table 4-2 S Series Signals, Host receptacle column, row S28; pp. 14-16 port/detection definitions; p. 13, Table 4-3 E Series Signals, Host receptacle column, row E1; pp. 14-16 port/detection definitions; p. 13, Table 4-3 E Series Signals, Host receptacle column, row E2; pp. 14-16 port/detection definitions; p. 13, Table 4-3 E Series Signals, Host receptacle column, row E3; pp. 14-16 port/detection definitions; p. 13, Table 4-3 E Series Signals, Host receptacle column, row E4; pp. 14-16 port/detection definitions; p. 13, Table 4-3 E Series Signals, Host receptacle column, row E5; pp. 14-16 port/detection definitions; p. 13, Table 4-3 E Series Signals, Host receptacle column, row E6; pp. 14-16 port/detection definitions; p. 13, Table 4-3 E Series Signals, Host receptacle column, row E7; pp. 14-16 port/detection definitions; p. 13, Table 4-3 E Series Signals, Host receptacle column, row E8; pp. 14-16 port/detection definitions; p. 13, Table 4-3 E Series Signals, Host receptacle column, row E9; pp. 14-16 port/detection definitions; p. 13, Table 4-3 E Series Signals, Host receptacle column, row E10; pp. 14-16 port/detection definitions; p. 13, Table 4-3 E Series Signals, Host receptacle column, row E11; pp. 14-16 port/detection definitions; p. 13, Table 4-3 E Series Signals, Host receptacle column, row E12; pp. 14-16 port/detection definitions; p. 13, Table 4-3 E Series Signals, Host receptacle column, row E13; pp. 14-16 port/detection definitions; p. 13, Table 4-3 E Series Signals, Host receptacle column, row E14; pp. 14-16 port/detection definitions; p. 13, Table 4-3 E Series Signals, Host receptacle column, row E15; pp. 14-16 port/detection definitions; p. 13, Table 4-3 E Series Signals, Host receptacle column, row E16; pp. 14-16 port/detection definitions; p. 13, Table 4-3 E Series Signals, Host receptacle column, row E17; pp. 14-16 port/detection definitions; p. 13, Table 4-3 E Series Signals, Host receptacle column, row E18; pp. 14-16 port/detection definitions; p. 13, Table 4-3 E Series Signals, Host receptacle column, row E19; pp. 14-16 port/detection definitions; p. 13, Table 4-3 E Series Signals, Host receptacle column, row E20; pp. 14-16 port/detection definitions; p. 13, Table 4-3 E Series Signals, Host receptacle column, row E21; pp. 14-16 port/detection definitions; p. 13, Table 4-3 E Series Signals, Host receptacle column, row E22; pp. 14-16 port/detection definitions; p. 13, Table 4-3 E Series Signals, Host receptacle column, row E23; pp. 14-16 port/detection definitions; p. 13, Table 4-3 E Series Signals, Host receptacle column, row E24; pp. 14-16 port/detection definitions; p. 13, Table 4-3 E Series Signals, Host receptacle column, row E25; pp. 14-16 port/detection definitions
S777 · SNIA SFF TA TWG · SFF-8639: Multifunction 6X Unshielded Connector
Rev 2.2, May 6, 2024 · p. 22 section 6.1 and Figure 6-1 Contact Numbering Scheme; p. 15 Figure 5-1 Device Free (Plug) Connector

U.3 / SFF-TA-1001 PCIe device plug

View and evidence limits

Use the separate host-receptacle/device-plug columns. PET/PER on a device still use host-perspective naming; E6 and S15 differ between host and device.

P198 U.2 / U.3 — **Agree** on comparable PCIe lane placement; **partial for sidebands/modes** — Both read **the same SFF-TA-1001 rev 1.1 and SFF-9639 rev 2.2 documents**, with matching hashes. U.3 PCIe-device assignments and the same 11 blank cells agree. U.2 puts lane 0 on E10/E11/E13/E14 and lane 3 on E17/E18/E20/E21; U.3 relocates PCIe lanes to S2-S27. A adds Wilder's U.2 test fixture; B adds Seagate Nytro 5060 and a separate U.3 universal-host column. Host/device E6 and S15, reserved versus fixture-defined HPT roles, and unused power/legacy-data contacts remain variant-specific. Shared SNIA evidence is not independent corroboration; Wilder and Seagate are additional, different device sources.
Single x4 PCIe lane numbers shown; dual-port use redistributes lane numbering. Blank source cells remain unverified.
SFF-9639 expressly warns in section 5 that its tables are a reference guide and the using-interface specifications are definitive. Blank cells were not converted to NC/reserved. The PCI-SIG U.2 module specification was not obtained in this pass.
Only the explicit SFF-TA-1001 host/PCIe device columns and single-x4 numbering are mapped. SAS/SATA protocol-specific uses, dual-x2 remaps, Gen-Z and NVMe-oF are not silently combined into those variants; Tables 4-4/4-7 and SFF-9639 Table 6-1 must be followed for the selected mode.

Schematic only · physical contact positions unconfirmed. Original drawing · not to scale. Scroll sideways if needed.

U.3 / SFF-TA-1001 PCIe device plug — source-scoped contact map
Pin	Signal	What it does	Status
P1	WAKE#	Control, detection or configuration connection; check the source and device.	Single source Sources
P2	Reserved	Reserved; no general-purpose wiring is established.	Single source Sources
P3	PWRDIS	Control, detection or configuration connection; check the source and device.	Single source Sources
P4	IfDet#	Control, detection or configuration connection; check the source and device.	Single source Sources
P5	Ground	Ground reference and return.	Single source Sources
P6	Ground	Ground reference and return.	Single source Sources
P7	Not confirmed	No settled assignment. Do not wire from this row.	Unverified Sources
P8	Not confirmed	No settled assignment. Do not wire from this row.	Unverified Sources
P9	Not confirmed	No settled assignment. Do not wire from this row.	Unverified Sources
P10	PRSNT#	Control, detection or configuration connection; check the source and device.	Single source Sources
P11	ACTIVITY#	Control, detection or configuration connection; check the source and device.	Single source Sources
P12	Ground	Ground reference and return.	Single source Sources
P13	+12V Precharge	Power connection (+12V Precharge). Check the specified supply.	Single source Sources
P14	+12V	Power connection (+12V). Check the specified supply.	Single source Sources
P15	+12V	Power connection (+12V). Check the specified supply.	Single source Sources
S1	Ground	Ground reference and return.	Single source Sources
S2	PETp0	Signal conductor. Pair, polarity and direction follow this named wiring.	Single source Sources
S3	PETn0	Signal conductor. Pair, polarity and direction follow this named wiring.	Single source Sources
S4	Ground	Ground reference and return.	Single source Sources
S5	PERn0	Signal conductor. Pair, polarity and direction follow this named wiring.	Single source Sources
S6	PERp0	Signal conductor. Pair, polarity and direction follow this named wiring.	Single source Sources
S7	Ground	Ground reference and return.	Single source Sources
S8	Ground	Ground reference and return.	Single source Sources
S9	PETp1	Signal conductor. Pair, polarity and direction follow this named wiring.	Single source Sources
S10	PETn1	Signal conductor. Pair, polarity and direction follow this named wiring.	Single source Sources
S11	Ground	Ground reference and return.	Single source Sources
S12	PERn1	Signal conductor. Pair, polarity and direction follow this named wiring.	Single source Sources
S13	PERp1	Signal conductor. Pair, polarity and direction follow this named wiring.	Single source Sources
S14	Ground	Ground reference and return.	Single source Sources
S15	HPT0	Control, detection or configuration connection; check the source and device.	Single source Sources
S16	Ground	Ground reference and return.	Single source Sources
S17	PETp2	Signal conductor. Pair, polarity and direction follow this named wiring.	Single source Sources
S18	PETn2	Signal conductor. Pair, polarity and direction follow this named wiring.	Single source Sources
S19	Ground	Ground reference and return.	Single source Sources
S20	PERn2	Signal conductor. Pair, polarity and direction follow this named wiring.	Single source Sources
S21	PERp2	Signal conductor. Pair, polarity and direction follow this named wiring.	Single source Sources
S22	Ground	Ground reference and return.	Single source Sources
S23	PETp3	Signal conductor. Pair, polarity and direction follow this named wiring.	Single source Sources
S24	PETn3	Signal conductor. Pair, polarity and direction follow this named wiring.	Single source Sources
S25	Ground	Ground reference and return.	Single source Sources
S26	PERn3	Signal conductor. Pair, polarity and direction follow this named wiring.	Single source Sources
S27	PERp3	Signal conductor. Pair, polarity and direction follow this named wiring.	Single source Sources
S28	Ground	Ground reference and return.	Single source Sources
E1	REFCLKB+	Clock or clock-control connection, as named by this source.	Single source Sources
E2	REFCLKB-	Clock or clock-control connection, as named by this source.	Single source Sources
E3	+3.3Vaux	Power connection (+3.3Vaux). Check the specified supply.	Single source Sources
E4	PERSTB#	Reset control; check active level and the named device.	Single source Sources
E5	PERST#	Reset control; check active level and the named device.	Single source Sources
E6	Ground	Ground reference and return.	Single source Sources
E7	REFCLK+	Clock or clock-control connection, as named by this source.	Single source Sources
E8	REFCLK-	Clock or clock-control connection, as named by this source.	Single source Sources
E9	Ground	Ground reference and return.	Single source Sources
E10	Not confirmed	No settled assignment. Do not wire from this row.	Unverified Sources
E11	Not confirmed	No settled assignment. Do not wire from this row.	Unverified Sources
E12	Ground	Ground reference and return.	Single source Sources
E13	Not confirmed	No settled assignment. Do not wire from this row.	Unverified Sources
E14	Not confirmed	No settled assignment. Do not wire from this row.	Unverified Sources
E15	Ground	Ground reference and return.	Single source Sources
E16	HPT1	Control, detection or configuration connection; check the source and device.	Single source Sources
E17	Not confirmed	No settled assignment. Do not wire from this row.	Unverified Sources
E18	Not confirmed	No settled assignment. Do not wire from this row.	Unverified Sources
E19	Ground	Ground reference and return.	Single source Sources
E20	Not confirmed	No settled assignment. Do not wire from this row.	Unverified Sources
E21	Not confirmed	No settled assignment. Do not wire from this row.	Unverified Sources
E22	Ground	Ground reference and return.	Single source Sources
E23	SMBCLK	Clock or clock-control connection, as named by this source.	Single source Sources
E24	SMBDAT	Control, detection or configuration connection; check the source and device.	Single source Sources
E25	DualPortEn#	Control, detection or configuration connection; check the source and device.	Single source Sources

Sources (2)

S776 · SNIA SFF TA TWG · SFF-TA-1001: Universal x4 Link Definition for SFF-8639
Rev 1.1, May 28, 2018 | Rev. 1.1, May 28, 2018 · p. 12, Table 4-1 P Series Signals, SFF-TA-1001 device plug / PCIe column, row P1; pp. 14-16 port/detection definitions; p. 12, Table 4-1 P Series Signals, SFF-TA-1001 device plug / PCIe column, row P2; pp. 14-16 port/detection definitions; p. 12, Table 4-1 P Series Signals, SFF-TA-1001 device plug / PCIe column, row P3; pp. 14-16 port/detection definitions; p. 12, Table 4-1 P Series Signals, SFF-TA-1001 device plug / PCIe column, row P4; pp. 14-16 port/detection definitions; p. 12, Table 4-1 P Series Signals, SFF-TA-1001 device plug / PCIe column, row P5; pp. 14-16 port/detection definitions; p. 12, Table 4-1 P Series Signals, SFF-TA-1001 device plug / PCIe column, row P6; pp. 14-16 port/detection definitions; p. 12, Table 4-1 P Series Signals, SFF-TA-1001 device plug / PCIe column, row P7; pp. 14-16 port/detection definitions; p. 12, Table 4-1 P Series Signals, SFF-TA-1001 device plug / PCIe column, row P8; pp. 14-16 port/detection definitions; p. 12, Table 4-1 P Series Signals, SFF-TA-1001 device plug / PCIe column, row P9; pp. 14-16 port/detection definitions; p. 12, Table 4-1 P Series Signals, SFF-TA-1001 device plug / PCIe column, row P10; pp. 14-16 port/detection definitions; p. 12, Table 4-1 P Series Signals, SFF-TA-1001 device plug / PCIe column, row P11; pp. 14-16 port/detection definitions; p. 12, Table 4-1 P Series Signals, SFF-TA-1001 device plug / PCIe column, row P12; pp. 14-16 port/detection definitions; p. 12, Table 4-1 P Series Signals, SFF-TA-1001 device plug / PCIe column, row P13; pp. 14-16 port/detection definitions; p. 12, Table 4-1 P Series Signals, SFF-TA-1001 device plug / PCIe column, row P14; pp. 14-16 port/detection definitions; p. 12, Table 4-1 P Series Signals, SFF-TA-1001 device plug / PCIe column, row P15; pp. 14-16 port/detection definitions; p. 12, Table 4-2 S Series Signals, SFF-TA-1001 device plug / PCIe column, row S1; pp. 14-16 port/detection definitions; p. 12, Table 4-2 S Series Signals, SFF-TA-1001 device plug / PCIe column, row S2; pp. 14-16 port/detection definitions; p. 12, Table 4-2 S Series Signals, SFF-TA-1001 device plug / PCIe column, row S3; pp. 14-16 port/detection definitions; p. 12, Table 4-2 S Series Signals, SFF-TA-1001 device plug / PCIe column, row S4; pp. 14-16 port/detection definitions; p. 12, Table 4-2 S Series Signals, SFF-TA-1001 device plug / PCIe column, row S5; pp. 14-16 port/detection definitions; p. 12, Table 4-2 S Series Signals, SFF-TA-1001 device plug / PCIe column, row S6; pp. 14-16 port/detection definitions; p. 12, Table 4-2 S Series Signals, SFF-TA-1001 device plug / PCIe column, row S7; pp. 14-16 port/detection definitions; p. 12, Table 4-2 S Series Signals, SFF-TA-1001 device plug / PCIe column, row S8; pp. 14-16 port/detection definitions; p. 12, Table 4-2 S Series Signals, SFF-TA-1001 device plug / PCIe column, row S9; pp. 14-16 port/detection definitions; p. 12, Table 4-2 S Series Signals, SFF-TA-1001 device plug / PCIe column, row S10; pp. 14-16 port/detection definitions; p. 12, Table 4-2 S Series Signals, SFF-TA-1001 device plug / PCIe column, row S11; pp. 14-16 port/detection definitions; p. 12, Table 4-2 S Series Signals, SFF-TA-1001 device plug / PCIe column, row S12; pp. 14-16 port/detection definitions; p. 12, Table 4-2 S Series Signals, SFF-TA-1001 device plug / PCIe column, row S13; pp. 14-16 port/detection definitions; p. 12, Table 4-2 S Series Signals, SFF-TA-1001 device plug / PCIe column, row S14; pp. 14-16 port/detection definitions; p. 12, Table 4-2 S Series Signals, SFF-TA-1001 device plug / PCIe column, row S15; pp. 14-16 port/detection definitions; p. 12, Table 4-2 S Series Signals, SFF-TA-1001 device plug / PCIe column, row S16; pp. 14-16 port/detection definitions; p. 12, Table 4-2 S Series Signals, SFF-TA-1001 device plug / PCIe column, row S17; pp. 14-16 port/detection definitions; p. 12, Table 4-2 S Series Signals, SFF-TA-1001 device plug / PCIe column, row S18; pp. 14-16 port/detection definitions; p. 12, Table 4-2 S Series Signals, SFF-TA-1001 device plug / PCIe column, row S19; pp. 14-16 port/detection definitions; p. 12, Table 4-2 S Series Signals, SFF-TA-1001 device plug / PCIe column, row S20; pp. 14-16 port/detection definitions; p. 12, Table 4-2 S Series Signals, SFF-TA-1001 device plug / PCIe column, row S21; pp. 14-16 port/detection definitions; p. 12, Table 4-2 S Series Signals, SFF-TA-1001 device plug / PCIe column, row S22; pp. 14-16 port/detection definitions; p. 12, Table 4-2 S Series Signals, SFF-TA-1001 device plug / PCIe column, row S23; pp. 14-16 port/detection definitions; p. 12, Table 4-2 S Series Signals, SFF-TA-1001 device plug / PCIe column, row S24; pp. 14-16 port/detection definitions; p. 12, Table 4-2 S Series Signals, SFF-TA-1001 device plug / PCIe column, row S25; pp. 14-16 port/detection definitions; p. 12, Table 4-2 S Series Signals, SFF-TA-1001 device plug / PCIe column, row S26; pp. 14-16 port/detection definitions; p. 12, Table 4-2 S Series Signals, SFF-TA-1001 device plug / PCIe column, row S27; pp. 14-16 port/detection definitions; p. 12, Table 4-2 S Series Signals, SFF-TA-1001 device plug / PCIe column, row S28; pp. 14-16 port/detection definitions; p. 13, Table 4-3 E Series Signals, SFF-TA-1001 device plug / PCIe column, row E1; pp. 14-16 port/detection definitions; p. 13, Table 4-3 E Series Signals, SFF-TA-1001 device plug / PCIe column, row E2; pp. 14-16 port/detection definitions; p. 13, Table 4-3 E Series Signals, SFF-TA-1001 device plug / PCIe column, row E3; pp. 14-16 port/detection definitions; p. 13, Table 4-3 E Series Signals, SFF-TA-1001 device plug / PCIe column, row E4; pp. 14-16 port/detection definitions; p. 13, Table 4-3 E Series Signals, SFF-TA-1001 device plug / PCIe column, row E5; pp. 14-16 port/detection definitions; p. 13, Table 4-3 E Series Signals, SFF-TA-1001 device plug / PCIe column, row E6; pp. 14-16 port/detection definitions; p. 13, Table 4-3 E Series Signals, SFF-TA-1001 device plug / PCIe column, row E7; pp. 14-16 port/detection definitions; p. 13, Table 4-3 E Series Signals, SFF-TA-1001 device plug / PCIe column, row E8; pp. 14-16 port/detection definitions; p. 13, Table 4-3 E Series Signals, SFF-TA-1001 device plug / PCIe column, row E9; pp. 14-16 port/detection definitions; p. 13, Table 4-3 E Series Signals, SFF-TA-1001 device plug / PCIe column, row E10; pp. 14-16 port/detection definitions; p. 13, Table 4-3 E Series Signals, SFF-TA-1001 device plug / PCIe column, row E11; pp. 14-16 port/detection definitions; p. 13, Table 4-3 E Series Signals, SFF-TA-1001 device plug / PCIe column, row E12; pp. 14-16 port/detection definitions; p. 13, Table 4-3 E Series Signals, SFF-TA-1001 device plug / PCIe column, row E13; pp. 14-16 port/detection definitions; p. 13, Table 4-3 E Series Signals, SFF-TA-1001 device plug / PCIe column, row E14; pp. 14-16 port/detection definitions; p. 13, Table 4-3 E Series Signals, SFF-TA-1001 device plug / PCIe column, row E15; pp. 14-16 port/detection definitions; p. 13, Table 4-3 E Series Signals, SFF-TA-1001 device plug / PCIe column, row E16; pp. 14-16 port/detection definitions; p. 13, Table 4-3 E Series Signals, SFF-TA-1001 device plug / PCIe column, row E17; pp. 14-16 port/detection definitions; p. 13, Table 4-3 E Series Signals, SFF-TA-1001 device plug / PCIe column, row E18; pp. 14-16 port/detection definitions; p. 13, Table 4-3 E Series Signals, SFF-TA-1001 device plug / PCIe column, row E19; pp. 14-16 port/detection definitions; p. 13, Table 4-3 E Series Signals, SFF-TA-1001 device plug / PCIe column, row E20; pp. 14-16 port/detection definitions; p. 13, Table 4-3 E Series Signals, SFF-TA-1001 device plug / PCIe column, row E21; pp. 14-16 port/detection definitions; p. 13, Table 4-3 E Series Signals, SFF-TA-1001 device plug / PCIe column, row E22; pp. 14-16 port/detection definitions; p. 13, Table 4-3 E Series Signals, SFF-TA-1001 device plug / PCIe column, row E23; pp. 14-16 port/detection definitions; p. 13, Table 4-3 E Series Signals, SFF-TA-1001 device plug / PCIe column, row E24; pp. 14-16 port/detection definitions; p. 13, Table 4-3 E Series Signals, SFF-TA-1001 device plug / PCIe column, row E25; pp. 14-16 port/detection definitions
S777 · SNIA SFF TA TWG · SFF-8639: Multifunction 6X Unshielded Connector
Rev 2.2, May 6, 2024 · p. 22 section 6.1 and Figure 6-1 Contact Numbering Scheme; p. 15 Figure 5-1 Device Free (Plug) Connector

Seagate Nytro 5060 2.5-inch U.2 device (named model family)

Device-specific wiring. Check your device’s manual before connecting or applying power.

View and evidence limits

Device manual Table 23 contact numbers. SG1/SG2 are separate ground features and are not counted among the 68 P/S/E contacts.

P198 U.2 / U.3 — **Agree** on comparable PCIe lane placement; **partial for sidebands/modes** — Both read **the same SFF-TA-1001 rev 1.1 and SFF-9639 rev 2.2 documents**, with matching hashes. U.3 PCIe-device assignments and the same 11 blank cells agree. U.2 puts lane 0 on E10/E11/E13/E14 and lane 3 on E17/E18/E20/E21; U.3 relocates PCIe lanes to S2-S27. A adds Wilder's U.2 test fixture; B adds Seagate Nytro 5060 and a separate U.3 universal-host column. Host/device E6 and S15, reserved versus fixture-defined HPT roles, and unused power/legacy-data contacts remain variant-specific. Shared SNIA evidence is not independent corroboration; Wilder and Seagate are additional, different device sources.
Device-specific implementation; do not use it as a universal U.2/U.3 replacement.
SFF-9639 expressly warns in section 5 that its tables are a reference guide and the using-interface specifications are definitive. Blank cells were not converted to NC/reserved. The PCI-SIG U.2 module specification was not obtained in this pass.
Only the explicit SFF-TA-1001 host/PCIe device columns and single-x4 numbering are mapped. SAS/SATA protocol-specific uses, dual-x2 remaps, Gen-Z and NVMe-oF are not silently combined into those variants; Tables 4-4/4-7 and SFF-9639 Table 6-1 must be followed for the selected mode.

Schematic only · physical contact positions unconfirmed. Original drawing · not to scale. Scroll sideways if needed.

Seagate Nytro 5060 2.5-inch U.2 device (named model family) — source-scoped contact map
Pin	Signal	What it does	Status
P1	Not confirmed	No settled assignment. Do not wire from this row.	Unverified Sources
P2	Reserved	Reserved; no general-purpose wiring is established.	Device-specific Sources
P3	PWRDIS	Control, detection or configuration connection; check the source and device.	Device-specific Sources
P4	IfDet#	Control, detection or configuration connection; check the source and device.	Device-specific Sources
P5	Ground	Ground reference and return.	Device-specific Sources
P6	Ground	Ground reference and return.	Device-specific Sources
P7	NC	Not connected or absent in this named wiring.	Not connected Sources
P8	NC	Not connected or absent in this named wiring.	Not connected Sources
P9	NC	Not connected or absent in this named wiring.	Not connected Sources
P10	PRSNT#	Control, detection or configuration connection; check the source and device.	Device-specific Sources
P11	ACTIVITY#	Control, detection or configuration connection; check the source and device.	Device-specific Sources
P12	Ground	Ground reference and return.	Device-specific Sources
P13	+12V Precharge	Power connection (+12V Precharge). Check the specified supply.	Device-specific Sources
P14	+12V	Power connection (+12V). Check the specified supply.	Device-specific Sources
P15	+12V	Power connection (+12V). Check the specified supply.	Device-specific Sources
S1	Ground	Ground reference and return.	Device-specific Sources
S2	NC	Not connected or absent in this named wiring.	Not connected Sources
S3	NC	Not connected or absent in this named wiring.	Not connected Sources
S4	Ground	Ground reference and return.	Device-specific Sources
S5	NC	Not connected or absent in this named wiring.	Not connected Sources
S6	NC	Not connected or absent in this named wiring.	Not connected Sources
S7	Ground	Ground reference and return.	Device-specific Sources
S8	Ground	Ground reference and return.	Device-specific Sources
S9	NC	Not connected or absent in this named wiring.	Not connected Sources
S10	NC	Not connected or absent in this named wiring.	Not connected Sources
S11	Ground	Ground reference and return.	Device-specific Sources
S12	NC	Not connected or absent in this named wiring.	Not connected Sources
S13	NC	Not connected or absent in this named wiring.	Not connected Sources
S14	Ground	Ground reference and return.	Device-specific Sources
S15	HPT0	Control, detection or configuration connection; check the source and device.	Device-specific Sources
S16	Ground	Ground reference and return.	Device-specific Sources
S17	U.2 TX p1	Signal conductor. Pair, polarity and direction follow this named wiring.	Device-specific Sources
S18	U.2 TX n1	Signal conductor. Pair, polarity and direction follow this named wiring.	Device-specific Sources
S19	Ground	Ground reference and return.	Device-specific Sources
S20	U.2 RX n1	Signal conductor. Pair, polarity and direction follow this named wiring.	Device-specific Sources
S21	U.2 RX p1	Signal conductor. Pair, polarity and direction follow this named wiring.	Device-specific Sources
S22	Ground	Ground reference and return.	Device-specific Sources
S23	U.2 TX p2	Signal conductor. Pair, polarity and direction follow this named wiring.	Device-specific Sources
S24	U.2 TX n2	Signal conductor. Pair, polarity and direction follow this named wiring.	Device-specific Sources
S25	Ground	Ground reference and return.	Device-specific Sources
S26	U.2 RX n2	Signal conductor. Pair, polarity and direction follow this named wiring.	Device-specific Sources
S27	U.2 RX p2	Signal conductor. Pair, polarity and direction follow this named wiring.	Device-specific Sources
S28	Ground	Ground reference and return.	Device-specific Sources
E1	REFCLKB+	Clock or clock-control connection, as named by this source.	Device-specific Sources
E2	REFCLKB-	Clock or clock-control connection, as named by this source.	Device-specific Sources
E3	+3.3Vaux	Power connection (+3.3Vaux). Check the specified supply.	Device-specific Sources
E4	CLKREQ#/PERSTB#	Reset control; check active level and the named device.	Device-specific Sources
E5	PERST#	Reset control; check active level and the named device.	Device-specific Sources
E6	IFDet2#	Control, detection or configuration connection; check the source and device.	Device-specific Sources
E7	REFCLK+	Clock or clock-control connection, as named by this source.	Device-specific Sources
E8	REFCLK-	Clock or clock-control connection, as named by this source.	Device-specific Sources
E9	Ground	Ground reference and return.	Device-specific Sources
E10	U.2 TX p0	Signal conductor. Pair, polarity and direction follow this named wiring.	Device-specific Sources
E11	U.2 TX n0	Signal conductor. Pair, polarity and direction follow this named wiring.	Device-specific Sources
E12	Ground	Ground reference and return.	Device-specific Sources
E13	U.2 RX n0	Signal conductor. Pair, polarity and direction follow this named wiring.	Device-specific Sources
E14	U.2 RX p0	Signal conductor. Pair, polarity and direction follow this named wiring.	Device-specific Sources
E15	Ground	Ground reference and return.	Device-specific Sources
E16	HPT1	Control, detection or configuration connection; check the source and device.	Device-specific Sources
E17	U.2 TX p3	Signal conductor. Pair, polarity and direction follow this named wiring.	Device-specific Sources
E18	U.2 TX n3	Signal conductor. Pair, polarity and direction follow this named wiring.	Device-specific Sources
E19	Ground	Ground reference and return.	Device-specific Sources
E20	U.2 RX n3	Signal conductor. Pair, polarity and direction follow this named wiring.	Device-specific Sources
E21	U.2 RX p3	Signal conductor. Pair, polarity and direction follow this named wiring.	Device-specific Sources
E22	Ground	Ground reference and return.	Device-specific Sources
E23	SMBCLK	Clock or clock-control connection, as named by this source.	Device-specific Sources
E24	SMBDAT	Control, detection or configuration connection; check the source and device.	Device-specific Sources
E25	DualPortEn#	Control, detection or configuration connection; check the source and device.	Device-specific Sources

Sources (2)

S778 · Seagate Technology LLC · Nytro 5060 NVMe 2.5-inch SSD Product Manual
208169400, Rev B, February 2025 · p. 52, section 9.5.5 Table 23 Connector SFF-8639 Pin Assignment and Descriptions, row P1; p. 52, section 9.5.5 Table 23 Connector SFF-8639 Pin Assignment and Descriptions, row P2; p. 52, section 9.5.5 Table 23 Connector SFF-8639 Pin Assignment and Descriptions, row P3; p. 52, section 9.5.5 Table 23 Connector SFF-8639 Pin Assignment and Descriptions, row P4; p. 52, section 9.5.5 Table 23 Connector SFF-8639 Pin Assignment and Descriptions, row P5; p. 52, section 9.5.5 Table 23 Connector SFF-8639 Pin Assignment and Descriptions, row P6; p. 52, section 9.5.5 Table 23 Connector SFF-8639 Pin Assignment and Descriptions, row P7; p. 52, section 9.5.5 Table 23 Connector SFF-8639 Pin Assignment and Descriptions, row P8; p. 52, section 9.5.5 Table 23 Connector SFF-8639 Pin Assignment and Descriptions, row P9; p. 52, section 9.5.5 Table 23 Connector SFF-8639 Pin Assignment and Descriptions, row P10; p. 52, section 9.5.5 Table 23 Connector SFF-8639 Pin Assignment and Descriptions, row P11; p. 52, section 9.5.5 Table 23 Connector SFF-8639 Pin Assignment and Descriptions, row P12; p. 52, section 9.5.5 Table 23 Connector SFF-8639 Pin Assignment and Descriptions, row P13; p. 52, section 9.5.5 Table 23 Connector SFF-8639 Pin Assignment and Descriptions, row P14; p. 52, section 9.5.5 Table 23 Connector SFF-8639 Pin Assignment and Descriptions, row P15; p. 52, section 9.5.5 Table 23 Connector SFF-8639 Pin Assignment and Descriptions, row S1; p. 52, section 9.5.5 Table 23 Connector SFF-8639 Pin Assignment and Descriptions, row S2; p. 52, section 9.5.5 Table 23 Connector SFF-8639 Pin Assignment and Descriptions, row S3; p. 52, section 9.5.5 Table 23 Connector SFF-8639 Pin Assignment and Descriptions, row S4; p. 52, section 9.5.5 Table 23 Connector SFF-8639 Pin Assignment and Descriptions, row S5; p. 52, section 9.5.5 Table 23 Connector SFF-8639 Pin Assignment and Descriptions, row S6; p. 52, section 9.5.5 Table 23 Connector SFF-8639 Pin Assignment and Descriptions, row S7; p. 52, section 9.5.5 Table 23 Connector SFF-8639 Pin Assignment and Descriptions, row S8; p. 52, section 9.5.5 Table 23 Connector SFF-8639 Pin Assignment and Descriptions, row S9; p. 52, section 9.5.5 Table 23 Connector SFF-8639 Pin Assignment and Descriptions, row S10; p. 52, section 9.5.5 Table 23 Connector SFF-8639 Pin Assignment and Descriptions, row S11; p. 52, section 9.5.5 Table 23 Connector SFF-8639 Pin Assignment and Descriptions, row S12; p. 52, section 9.5.5 Table 23 Connector SFF-8639 Pin Assignment and Descriptions, row S13; p. 52, section 9.5.5 Table 23 Connector SFF-8639 Pin Assignment and Descriptions, row S14; p. 52, section 9.5.5 Table 23 Connector SFF-8639 Pin Assignment and Descriptions, row S15; p. 52, section 9.5.5 Table 23 Connector SFF-8639 Pin Assignment and Descriptions, row S16; p. 52, section 9.5.5 Table 23 Connector SFF-8639 Pin Assignment and Descriptions, row S17; p. 52, section 9.5.5 Table 23 Connector SFF-8639 Pin Assignment and Descriptions, row S18; p. 52, section 9.5.5 Table 23 Connector SFF-8639 Pin Assignment and Descriptions, row S19; p. 52, section 9.5.5 Table 23 Connector SFF-8639 Pin Assignment and Descriptions, row S20; p. 53, section 9.5.5 Table 23 Connector SFF-8639 Pin Assignment and Descriptions, row S21; p. 53, section 9.5.5 Table 23 Connector SFF-8639 Pin Assignment and Descriptions, row S22; p. 53, section 9.5.5 Table 23 Connector SFF-8639 Pin Assignment and Descriptions, row S23; p. 53, section 9.5.5 Table 23 Connector SFF-8639 Pin Assignment and Descriptions, row S24; p. 53, section 9.5.5 Table 23 Connector SFF-8639 Pin Assignment and Descriptions, row S25; p. 53, section 9.5.5 Table 23 Connector SFF-8639 Pin Assignment and Descriptions, row S26; p. 53, section 9.5.5 Table 23 Connector SFF-8639 Pin Assignment and Descriptions, row S27; p. 53, section 9.5.5 Table 23 Connector SFF-8639 Pin Assignment and Descriptions, row S28; p. 53, section 9.5.5 Table 23 Connector SFF-8639 Pin Assignment and Descriptions, row E1; p. 53, section 9.5.5 Table 23 Connector SFF-8639 Pin Assignment and Descriptions, row E2; p. 53, section 9.5.5 Table 23 Connector SFF-8639 Pin Assignment and Descriptions, row E3; p. 53, section 9.5.5 Table 23 Connector SFF-8639 Pin Assignment and Descriptions, row E4; p. 53, section 9.5.5 Table 23 Connector SFF-8639 Pin Assignment and Descriptions, row E5; p. 53, section 9.5.5 Table 23 Connector SFF-8639 Pin Assignment and Descriptions, row E6; p. 53, section 9.5.5 Table 23 Connector SFF-8639 Pin Assignment and Descriptions, row E7; p. 53, section 9.5.5 Table 23 Connector SFF-8639 Pin Assignment and Descriptions, row E8; p. 53, section 9.5.5 Table 23 Connector SFF-8639 Pin Assignment and Descriptions, row E9; p. 53, section 9.5.5 Table 23 Connector SFF-8639 Pin Assignment and Descriptions, row E10; p. 53, section 9.5.5 Table 23 Connector SFF-8639 Pin Assignment and Descriptions, row E11; p. 53, section 9.5.5 Table 23 Connector SFF-8639 Pin Assignment and Descriptions, row E12; p. 53, section 9.5.5 Table 23 Connector SFF-8639 Pin Assignment and Descriptions, row E13; p. 53, section 9.5.5 Table 23 Connector SFF-8639 Pin Assignment and Descriptions, row E14; p. 53, section 9.5.5 Table 23 Connector SFF-8639 Pin Assignment and Descriptions, row E15; p. 53, section 9.5.5 Table 23 Connector SFF-8639 Pin Assignment and Descriptions, row E16; p. 53, section 9.5.5 Table 23 Connector SFF-8639 Pin Assignment and Descriptions, row E17; p. 53, section 9.5.5 Table 23 Connector SFF-8639 Pin Assignment and Descriptions, row E18; p. 53, section 9.5.5 Table 23 Connector SFF-8639 Pin Assignment and Descriptions, row E19; p. 53, section 9.5.5 Table 23 Connector SFF-8639 Pin Assignment and Descriptions, row E20; p. 53, section 9.5.5 Table 23 Connector SFF-8639 Pin Assignment and Descriptions, row E21; p. 53, section 9.5.5 Table 23 Connector SFF-8639 Pin Assignment and Descriptions, row E22; p. 53, section 9.5.5 Table 23 Connector SFF-8639 Pin Assignment and Descriptions, row E23; p. 53, section 9.5.5 Table 23 Connector SFF-8639 Pin Assignment and Descriptions, row E24; p. 53, section 9.5.5 Table 23 Connector SFF-8639 Pin Assignment and Descriptions, row E25
S777 · SNIA SFF TA TWG · SFF-8639: Multifunction 6X Unshielded Connector
Rev 2.2, May 6, 2024 · p. 22 section 6.1 and Figure 6-1 Contact Numbering Scheme; p. 15 Figure 5-1 Device Free (Plug) Connector

What is not established

This field note does not approve a connection, adapter, cable assembly, rewiring scheme or fabricated part. It intentionally omits unsupported pin assignments and mechanical tolerances.

Storage recognition: next evidence check

Match the exact drive, backplane, controller and cable to the applicable interface documentation. Keep U.2 and U.3 routing questions open until then. The exterior alone does not identify U.2 versus U.3, certify lane routing or authorize an adapter or live connection. Sources: C198B, C198C, C198D, C198E. Original qualitative study; independent technical and rights review pending.

Your next step

Move from the form to the requirement.

Read the engineering reference Source-scoped details, orientation and explicit unknowns.Work through a connection Choose your task before deciding on a cable.Explore this evidence trail Inspect the claims and their dependencies.

The source trail

Evidence for this page

AI-assisted inspection is not independent engineering review. Source scope and access limitations are disclosed below. Procedural checklists are editorial requirements, not hardware measurements.

Back to first citation ↑

C198ASource checked · pending review

Amphenol identifies its SAS/PCIe U.2/U.3 connector series as a 68-position interface compatible with SFF-8639.

Amphenol Communications Solutions · SAS/PCIe 5.0 U.2/U.3 connector series ↗

Locator: U.2/U.3 series overview
Access: public page. Identification/reference scope only. V36 does not convert this source into a universal pinout, fabrication drawing, electrical approval or end-to-end compatibility verdict.

S202: full source recordInspect review dependencies →

Claim scope: V36 catalogue-expansion identification fact only; not independent technical approval, fabrication data, wiring instruction or end-to-end compatibility proof.. Next review due 2027-01-03.

Back to first citation ↑

C198BSource checked · pending review

SFF-TA-8639 revision 2.2 defines a 68-contact system, while SFF-9639 explains that a device plug may populate only the contacts required by its use case.

SNIA · SNIA SFF-TA-8639 Multifunction 6X Unshielded Connector, revision 2.2 ↗

Locator: Rev 2.2, 2024-05-06. Sections 4.1 and 5.2; printed pp.15–16 Figures 5-1/5-2 visually inspected (PDF indices 14–15).
Access: public pdf text. No exact commercial component, U.2/U.3 system identification, signal routing, supported speed or live-mating approval established.

S599: full source record SNIA · SNIA SFF-9639 Multifunction 6X connector reference guide, revision 2.2 ↗

Locator: Rev 2.2, May 2, 2025. Page 5 section 1.1 and page 7 section 5 including the source-authority warning; page 7 visually inspected.
Access: public pdf text. Not a definitive current pinout. This guide explicitly warns that its tables can lag the interface standards; tables are not reproduced.

S600: full source recordInspect review dependencies →

Claim scope: V143: the named drawing/revision or exact product page only. Recognition and document-role evidence; not a pinout, adapter verdict, dimensioned mating gauge, electrical approval or current installed-device claim.. Next review due 2027-01-11.

Back to first citation ↑

C198CSource checked · pending review

The device plug in SFF-TA-8639 Figure 5-1 has contact areas on opposite faces and additional fine-contact regions; one front-facing photograph cannot show the whole interface.

SNIA · SNIA SFF-TA-8639 Multifunction 6X Unshielded Connector, revision 2.2 ↗

S599: full source recordInspect review dependencies →

Back to first citation ↑

C198DSource checked · pending review

SFF-TA-8639 revision 2.2 section 5.2 says its fixed-connector footprint is not generally a replacement for SFF-8482 or SFF-8630 footprints.

SNIA · SNIA SFF-TA-8639 Multifunction 6X Unshielded Connector, revision 2.2 ↗

S599: full source recordInspect review dependencies →

Back to first citation ↑

C198ESource checked · pending review

SFF-9639 revision 2.2 is informational and directs readers to the using-interface standards for definitive signal definitions; it warns that its own tables may become inaccurate.

SNIA · SNIA SFF-9639 Multifunction 6X connector reference guide, revision 2.2 ↗

S600: full source recordInspect review dependencies →

Suggest a correction to this field note →

Put this field note to work.

Add to discovery trayRecord an unsaved candidate

Candidate selection does not confirm the identity or capabilities of your physical item.

Evidence behind this page

Scope first. Source second. Approval separate.

3 linked sources · 5 scoped claims · 0 sources with inspection/access flags.

Page scope: catalogue_expansion_v36

Assessment 2026-10-22 · earliest scheduled source review 2027-01-03. This is a recorded-date assessment, not a live source check. Page-level independent review is not established by this panel.

Inspect 3 source scopes, access limits and dates

S202 · SAS/PCIe 5.0 U.2/U.3 connector series

Amphenol Communications Solutions · Manufacturer / product-owner domain · inspected 2026-10-05 · due 2027-01-03

Within inspection window

Scoped support: Identifies a 68-position SAS/PCIe U.2/U.3 connector series compatible with the SFF-8639 interface family.

Not established / limitations: Identification/reference scope only. V36 does not convert this source into a universal pinout, fabrication drawing, electrical approval or end-to-end compatibility verdict.

Locator: U.2/U.3 series overview

S599 · SNIA SFF-TA-8639 Multifunction 6X Unshielded Connector, revision 2.2

SNIA · Standards-organization domain · inspected 2026-10-13 · due 2027-01-11

Within inspection window

Scoped support: 68-contact specification-interface device plug, opposing contact faces and footprint limitations.

Not established / limitations: No exact commercial component, U.2/U.3 system identification, signal routing, supported speed or live-mating approval established.

Locator: Rev 2.2, 2024-05-06. Sections 4.1 and 5.2; printed pp.15–16 Figures 5-1/5-2 visually inspected (PDF indices 14–15).

S600 · SNIA SFF-9639 Multifunction 6X connector reference guide, revision 2.2

SNIA · Standards-organization domain · inspected 2026-10-13 · due 2027-01-11

Within inspection window

Scoped support: Informational guide versus authoritative using-interface standards; contact population depends on use case.

Not established / limitations: Not a definitive current pinout. This guide explicitly warns that its tables can lag the interface standards; tables are not reproduced.

Locator: Rev 2.2, May 2, 2025. Page 5 section 1.1 and page 7 section 5 including the source-authority warning; page 7 visually inspected.

Trace 5 claims to their source records

C198A · P198

Amphenol identifies its SAS/PCIe U.2/U.3 connector series as a 68-position interface compatible with SFF-8639.

Claim scope: V36 catalogue-expansion identification fact only; not independent technical approval, fabrication data, wiring instruction or end-to-end compatibility proof.

Source links: S202 · Evidence trail → (private workspace)

C198B · P198

SFF-TA-8639 revision 2.2 defines a 68-contact system, while SFF-9639 explains that a device plug may populate only the contacts required by its use case.

Claim scope: V143: the named drawing/revision or exact product page only. Recognition and document-role evidence; not a pinout, adapter verdict, dimensioned mating gauge, electrical approval or current installed-device claim.

Source links: S599 · S600 · Evidence trail → (private workspace)

C198C · P198

The device plug in SFF-TA-8639 Figure 5-1 has contact areas on opposite faces and additional fine-contact regions; one front-facing photograph cannot show the whole interface.

Source links: S599 · Evidence trail → (private workspace)

C198D · P198

SFF-TA-8639 revision 2.2 section 5.2 says its fixed-connector footprint is not generally a replacement for SFF-8482 or SFF-8630 footprints.

Source links: S599 · Evidence trail → (private workspace)

C198E · P198

SFF-9639 revision 2.2 is informational and directs readers to the using-interface standards for definitive signal definitions; it warns that its own tables may become inaccurate.

Source links: S600 · Evidence trail → (private workspace)

Prepare this page for review →Read the evidence method →

Recorded evidence only. An inspection date, publisher label, source link or generated packet is not independent technical review, hardware testing, fabrication approval or a compatibility verdict.

U.2 / U.3 SFF-8639 68-position drive connector

SFF-TA-8639 / U.2–U.3 context

Storage: role, interface, system

Recognize it. Then verify it.

Source-scoped identification facts

Specifications and limits

What to check

Pinout

Wilder PCIe Gen-5 U.2 Plug (CLB) test fixture

SNIA SFF-TA-1001 U.3 PCIe device plug, single port

U.2 / Quad PCIe plug — SNIA reference-guide use

U.3 / SFF-TA-1001 universal host receptacle

U.3 / SFF-TA-1001 PCIe device plug

Seagate Nytro 5060 2.5-inch U.2 device (named model family)

What is not established

Storage recognition: next evidence check

Move from the form to the requirement.

Evidence for this page

Related field notes

SAS SFF-8482 drive connector

SlimSAS connector family

M.2 card edge interface

Put this field note to work.

Scope first. Source second. Approval separate.

S202 · SAS/PCIe 5.0 U.2/U.3 connector series

S599 · SNIA SFF-TA-8639 Multifunction 6X Unshielded Connector, revision 2.2

S600 · SNIA SFF-9639 Multifunction 6X connector reference guide, revision 2.2

C198A · P198

C198B · P198

C198C · P198

C198D · P198

C198E · P198