U.2 / U.3 SFF-8639 68-position drive connector engineering reference

Wilder PCIe Gen-5 U.2 Plug (CLB) test fixture: original contact normalization. Statuses distinguish comparison agreement, source limits and named-device wiring.

Wilder Technologies, LLC · PCIe Gen-5 U.2 Test Adapters User Manual ↗
p.29, Table 5 PCIe Gen-5 U.2 Plug (CLB) Pin Assignments, all grouped and individual rows · Source scope and unresolved evidence are preserved in the engineering variant.

SNIA SFF TWG · SFF-9639: Reference Guide for Multifunction 6X Unshielded Connector Pinouts ↗
p. 7, Table 5-1 P Series Signals (Plug), Quad PCIe column, row P10; p. 7 section 5 reference-guide warning; p. 7, Table 5-1 P Series Signals (Plug), Quad PCIe column, row P11; p. 7 section 5 reference-guide warning; p. 7, Table 5-1 P Series Signals (Plug), Quad PCIe column, row P12; p. 7 section 5 reference-guide warning; p. 7, Table 5-1 P Series Signals (Plug), Quad PCIe column, row P13; p. 7 section 5 reference-guide warning; p. 7, Table 5-1 P Series Signals (Plug), Quad PCIe column, row P14; p. 7 section 5 reference-guide warning; p. 7, Table 5-1 P Series Signals (Plug), Quad PCIe column, row P15; p. 7 section 5 reference-guide warning; p. 7, Table 5-1 P Series Signals (Plug), Quad PCIe column, row P1; p. 7 section 5 reference-guide warning; p. 7, Table 5-1 P Series Signals (Plug), Quad PCIe column, row P2; p. 7 section 5 reference-guide warning; p. 7, Table 5-1 P Series Signals (Plug), Quad PCIe column, row P3; p. 7 section 5 reference-guide warning; p. 7, Table 5-1 P Series Signals (Plug), Quad PCIe column, row P4; p. 7 section 5 reference-guide warning; p. 7, Table 5-1 P Series Signals (Plug), Quad PCIe column, row P5; p. 7 section 5 reference-guide warning; p. 7, Table 5-1 P Series Signals (Plug), Quad PCIe column, row P6; p. 7 section 5 reference-guide warning; p. 7, Table 5-1 P Series Signals (Plug), Quad PCIe column, row P7; p. 7 section 5 reference-guide warning; p. 7, Table 5-1 P Series Signals (Plug), Quad PCIe column, row P8; p. 7 section 5 reference-guide warning; p. 7, Table 5-1 P Series Signals (Plug), Quad PCIe column, row P9; p. 7 section 5 reference-guide warning; p. 8, Table 5-2 S Series Signals (Plug), Quad PCIe column, row S10; p. 7 section 5 reference-guide warning; p. 8, Table 5-2 S Series Signals (Plug), Quad PCIe column, row S11; p. 7 section 5 reference-guide warning; p. 8, Table 5-2 S Series Signals (Plug), Quad PCIe column, row S12; p. 7 section 5 reference-guide warning; p. 8, Table 5-2 S Series Signals (Plug), Quad PCIe column, row S13; p. 7 section 5 reference-guide warning; p. 8, Table 5-2 S Series Signals (Plug), Quad PCIe column, row S14; p. 7 section 5 reference-guide warning; p. 8, Table 5-2 S Series Signals (Plug), Quad PCIe column, row S15; p. 7 section 5 reference-guide warning; p. 8, Table 5-2 S Series Signals (Plug), Quad PCIe column, row S16; p. 7 section 5 reference-guide warning; p. 8, Table 5-2 S Series Signals (Plug), Quad PCIe column, row S17; p. 7 section 5 reference-guide warning; p. 8, Table 5-2 S Series Signals (Plug), Quad PCIe column, row S18; p. 7 section 5 reference-guide warning; p. 8, Table 5-2 S Series Signals (Plug), Quad PCIe column, row S19; p. 7 section 5 reference-guide warning; p. 8, Table 5-2 S Series Signals (Plug), Quad PCIe column, row S1; p. 7 section 5 reference-guide warning; p. 8, Table 5-2 S Series Signals (Plug), Quad PCIe column, row S20; p. 7 section 5 reference-guide warning; p. 8, Table 5-2 S Series Signals (Plug), Quad PCIe column, row S21; p. 7 section 5 reference-guide warning; p. 8, Table 5-2 S Series Signals (Plug), Quad PCIe column, row S22; p. 7 section 5 reference-guide warning; p. 8, Table 5-2 S Series Signals (Plug), Quad PCIe column, row S23; p. 7 section 5 reference-guide warning; p. 8, Table 5-2 S Series Signals (Plug), Quad PCIe column, row S24; p. 7 section 5 reference-guide warning; p. 8, Table 5-2 S Series Signals (Plug), Quad PCIe column, row S25; p. 7 section 5 reference-guide warning; p. 8, Table 5-2 S Series Signals (Plug), Quad PCIe column, row S26; p. 7 section 5 reference-guide warning; p. 8, Table 5-2 S Series Signals (Plug), Quad PCIe column, row S27; p. 7 section 5 reference-guide warning; p. 8, Table 5-2 S Series Signals (Plug), Quad PCIe column, row S28; p. 7 section 5 reference-guide warning; p. 8, Table 5-2 S Series Signals (Plug), Quad PCIe column, row S2; p. 7 section 5 reference-guide warning; p. 8, Table 5-2 S Series Signals (Plug), Quad PCIe column, row S3; p. 7 section 5 reference-guide warning; p. 8, Table 5-2 S Series Signals (Plug), Quad PCIe column, row S4; p. 7 section 5 reference-guide warning; p. 8, Table 5-2 S Series Signals (Plug), Quad PCIe column, row S5; p. 7 section 5 reference-guide warning; p. 8, Table 5-2 S Series Signals (Plug), Quad PCIe column, row S6; p. 7 section 5 reference-guide warning; p. 8, Table 5-2 S Series Signals (Plug), Quad PCIe column, row S7; p. 7 section 5 reference-guide warning; p. 8, Table 5-2 S Series Signals (Plug), Quad PCIe column, row S8; p. 7 section 5 reference-guide warning; p. 8, Table 5-2 S Series Signals (Plug), Quad PCIe column, row S9; p. 7 section 5 reference-guide warning; p. 9, Table 5-3 E Series Signals (Plug), Quad PCIe column, row E10; p. 7 section 5 reference-guide warning; p. 9, Table 5-3 E Series Signals (Plug), Quad PCIe column, row E11; p. 7 section 5 reference-guide warning; p. 9, Table 5-3 E Series Signals (Plug), Quad PCIe column, row E12; p. 7 section 5 reference-guide warning; p. 9, Table 5-3 E Series Signals (Plug), Quad PCIe column, row E13; p. 7 section 5 reference-guide warning; p. 9, Table 5-3 E Series Signals (Plug), Quad PCIe column, row E14; p. 7 section 5 reference-guide warning; p. 9, Table 5-3 E Series Signals (Plug), Quad PCIe column, row E15; p. 7 section 5 reference-guide warning; p. 9, Table 5-3 E Series Signals (Plug), Quad PCIe column, row E16; p. 7 section 5 reference-guide warning; p. 9, Table 5-3 E Series Signals (Plug), Quad PCIe column, row E17; p. 7 section 5 reference-guide warning; p. 9, Table 5-3 E Series Signals (Plug), Quad PCIe column, row E18; p. 7 section 5 reference-guide warning; p. 9, Table 5-3 E Series Signals (Plug), Quad PCIe column, row E19; p. 7 section 5 reference-guide warning; p. 9, Table 5-3 E Series Signals (Plug), Quad PCIe column, row E1; p. 7 section 5 reference-guide warning; p. 9, Table 5-3 E Series Signals (Plug), Quad PCIe column, row E20; p. 7 section 5 reference-guide warning; p. 9, Table 5-3 E Series Signals (Plug), Quad PCIe column, row E21; p. 7 section 5 reference-guide warning; p. 9, Table 5-3 E Series Signals (Plug), Quad PCIe column, row E22; p. 7 section 5 reference-guide warning; p. 9, Table 5-3 E Series Signals (Plug), Quad PCIe column, row E23; p. 7 section 5 reference-guide warning; p. 9, Table 5-3 E Series Signals (Plug), Quad PCIe column, row E24; p. 7 section 5 reference-guide warning; p. 9, Table 5-3 E Series Signals (Plug), Quad PCIe column, row E25; p. 7 section 5 reference-guide warning; p. 9, Table 5-3 E Series Signals (Plug), Quad PCIe column, row E2; p. 7 section 5 reference-guide warning; p. 9, Table 5-3 E Series Signals (Plug), Quad PCIe column, row E3; p. 7 section 5 reference-guide warning; p. 9, Table 5-3 E Series Signals (Plug), Quad PCIe column, row E4; p. 7 section 5 reference-guide warning; p. 9, Table 5-3 E Series Signals (Plug), Quad PCIe column, row E5; p. 7 section 5 reference-guide warning; p. 9, Table 5-3 E Series Signals (Plug), Quad PCIe column, row E6; p. 7 section 5 reference-guide warning; p. 9, Table 5-3 E Series Signals (Plug), Quad PCIe column, row E7; p. 7 section 5 reference-guide warning; p. 9, Table 5-3 E Series Signals (Plug), Quad PCIe column, row E8; p. 7 section 5 reference-guide warning; p. 9, Table 5-3 E Series Signals (Plug), Quad PCIe column, row E9; p. 7 section 5 reference-guide warning; p.8, Table 5-2 PCIe naming note: receiver on device has transmitter signal name · Source scope and unresolved evidence are preserved in the engineering variant.

SNIA SFF-TA-1001 U.3 PCIe device plug, single port: original contact normalization. Statuses distinguish comparison agreement, source limits and named-device wiring.

SNIA SFF TA TWG · SFF-TA-1001: Universal x4 Link Definition for SFF-8639 ↗
p. 12, Table 4-1 P Series Signals, Host receptacle column, row P10; pp. 14-16 port/detection definitions; p. 12, Table 4-1 P Series Signals, Host receptacle column, row P11; pp. 14-16 port/detection definitions; p. 12, Table 4-1 P Series Signals, Host receptacle column, row P12; pp. 14-16 port/detection definitions; p. 12, Table 4-1 P Series Signals, Host receptacle column, row P13; pp. 14-16 port/detection definitions; p. 12, Table 4-1 P Series Signals, Host receptacle column, row P14; pp. 14-16 port/detection definitions; p. 12, Table 4-1 P Series Signals, Host receptacle column, row P15; pp. 14-16 port/detection definitions; p. 12, Table 4-1 P Series Signals, Host receptacle column, row P1; pp. 14-16 port/detection definitions; p. 12, Table 4-1 P Series Signals, Host receptacle column, row P2; pp. 14-16 port/detection definitions; p. 12, Table 4-1 P Series Signals, Host receptacle column, row P3; pp. 14-16 port/detection definitions; p. 12, Table 4-1 P Series Signals, Host receptacle column, row P4; pp. 14-16 port/detection definitions; p. 12, Table 4-1 P Series Signals, Host receptacle column, row P5; pp. 14-16 port/detection definitions; p. 12, Table 4-1 P Series Signals, Host receptacle column, row P6; pp. 14-16 port/detection definitions; p. 12, Table 4-1 P Series Signals, Host receptacle column, row P7; pp. 14-16 port/detection definitions; p. 12, Table 4-1 P Series Signals, Host receptacle column, row P8; pp. 14-16 port/detection definitions; p. 12, Table 4-1 P Series Signals, Host receptacle column, row P9; pp. 14-16 port/detection definitions; p. 12, Table 4-1 P Series Signals, SFF-TA-1001 device plug / PCIe column, row P10; pp. 14-16 port/detection definitions; p. 12, Table 4-1 P Series Signals, SFF-TA-1001 device plug / PCIe column, row P11; pp. 14-16 port/detection definitions; p. 12, Table 4-1 P Series Signals, SFF-TA-1001 device plug / PCIe column, row P12; pp. 14-16 port/detection definitions; p. 12, Table 4-1 P Series Signals, SFF-TA-1001 device plug / PCIe column, row P13; pp. 14-16 port/detection definitions; p. 12, Table 4-1 P Series Signals, SFF-TA-1001 device plug / PCIe column, row P14; pp. 14-16 port/detection definitions; p. 12, Table 4-1 P Series Signals, SFF-TA-1001 device plug / PCIe column, row P15; pp. 14-16 port/detection definitions; p. 12, Table 4-1 P Series Signals, SFF-TA-1001 device plug / PCIe column, row P1; pp. 14-16 port/detection definitions; p. 12, Table 4-1 P Series Signals, SFF-TA-1001 device plug / PCIe column, row P2; pp. 14-16 port/detection definitions; p. 12, Table 4-1 P Series Signals, SFF-TA-1001 device plug / PCIe column, row P3; pp. 14-16 port/detection definitions; p. 12, Table 4-1 P Series Signals, SFF-TA-1001 device plug / PCIe column, row P4; pp. 14-16 port/detection definitions; p. 12, Table 4-1 P Series Signals, SFF-TA-1001 device plug / PCIe column, row P5; pp. 14-16 port/detection definitions; p. 12, Table 4-1 P Series Signals, SFF-TA-1001 device plug / PCIe column, row P6; pp. 14-16 port/detection definitions; p. 12, Table 4-1 P Series Signals, SFF-TA-1001 device plug / PCIe column, row P7; pp. 14-16 port/detection definitions; p. 12, Table 4-1 P Series Signals, SFF-TA-1001 device plug / PCIe column, row P8; pp. 14-16 port/detection definitions; p. 12, Table 4-1 P Series Signals, SFF-TA-1001 device plug / PCIe column, row P9; pp. 14-16 port/detection definitions; p. 12, Table 4-2 S Series Signals, Host receptacle column, row S10; pp. 14-16 port/detection definitions; p. 12, Table 4-2 S Series Signals, Host receptacle column, row S11; pp. 14-16 port/detection definitions; p. 12, Table 4-2 S Series Signals, Host receptacle column, row S12; pp. 14-16 port/detection definitions; p. 12, Table 4-2 S Series Signals, Host receptacle column, row S13; pp. 14-16 port/detection definitions; p. 12, Table 4-2 S Series Signals, Host receptacle column, row S14; pp. 14-16 port/detection definitions; p. 12, Table 4-2 S Series Signals, Host receptacle column, row S15; pp. 14-16 port/detection definitions; p. 12, Table 4-2 S Series Signals, Host receptacle column, row S16; pp. 14-16 port/detection definitions; p. 12, Table 4-2 S Series Signals, Host receptacle column, row S17; pp. 14-16 port/detection definitions; p. 12, Table 4-2 S Series Signals, Host receptacle column, row S18; pp. 14-16 port/detection definitions; p. 12, Table 4-2 S Series Signals, Host receptacle column, row S19; pp. 14-16 port/detection definitions; p. 12, Table 4-2 S Series Signals, Host receptacle column, row S1; pp. 14-16 port/detection definitions; p. 12, Table 4-2 S Series Signals, Host receptacle column, row S20; pp. 14-16 port/detection definitions; p. 12, Table 4-2 S Series Signals, Host receptacle column, row S21; pp. 14-16 port/detection definitions; p. 12, Table 4-2 S Series Signals, Host receptacle column, row S22; pp. 14-16 port/detection definitions; p. 12, Table 4-2 S Series Signals, Host receptacle column, row S23; pp. 14-16 port/detection definitions; p. 12, Table 4-2 S Series Signals, Host receptacle column, row S24; pp. 14-16 port/detection definitions; p. 12, Table 4-2 S Series Signals, Host receptacle column, row S25; pp. 14-16 port/detection definitions; p. 12, Table 4-2 S Series Signals, Host receptacle column, row S26; pp. 14-16 port/detection definitions; p. 12, Table 4-2 S Series Signals, Host receptacle column, row S27; pp. 14-16 port/detection definitions; p. 12, Table 4-2 S Series Signals, Host receptacle column, row S28; pp. 14-16 port/detection definitions; p. 12, Table 4-2 S Series Signals, Host receptacle column, row S2; pp. 14-16 port/detection definitions; p. 12, Table 4-2 S Series Signals, Host receptacle column, row S3; pp. 14-16 port/detection definitions; p. 12, Table 4-2 S Series Signals, Host receptacle column, row S4; pp. 14-16 port/detection definitions; p. 12, Table 4-2 S Series Signals, Host receptacle column, row S5; pp. 14-16 port/detection definitions; p. 12, Table 4-2 S Series Signals, Host receptacle column, row S6; pp. 14-16 port/detection definitions; p. 12, Table 4-2 S Series Signals, Host receptacle column, row S7; pp. 14-16 port/detection definitions; p. 12, Table 4-2 S Series Signals, Host receptacle column, row S8; pp. 14-16 port/detection definitions; p. 12, Table 4-2 S Series Signals, Host receptacle column, row S9; pp. 14-16 port/detection definitions; p. 12, Table 4-2 S Series Signals, SFF-TA-1001 device plug / PCIe column, row S10; pp. 14-16 port/detection definitions; p. 12, Table 4-2 S Series Signals, SFF-TA-1001 device plug / PCIe column, row S11; pp. 14-16 port/detection definitions; p. 12, Table 4-2 S Series Signals, SFF-TA-1001 device plug / PCIe column, row S12; pp. 14-16 port/detection definitions; p. 12, Table 4-2 S Series Signals, SFF-TA-1001 device plug / PCIe column, row S13; pp. 14-16 port/detection definitions; p. 12, Table 4-2 S Series Signals, SFF-TA-1001 device plug / PCIe column, row S14; pp. 14-16 port/detection definitions; p. 12, Table 4-2 S Series Signals, SFF-TA-1001 device plug / PCIe column, row S15; pp. 14-16 port/detection definitions; p. 12, Table 4-2 S Series Signals, SFF-TA-1001 device plug / PCIe column, row S16; pp. 14-16 port/detection definitions; p. 12, Table 4-2 S Series Signals, SFF-TA-1001 device plug / PCIe column, row S17; pp. 14-16 port/detection definitions; p. 12, Table 4-2 S Series Signals, SFF-TA-1001 device plug / PCIe column, row S18; pp. 14-16 port/detection definitions; p. 12, Table 4-2 S Series Signals, SFF-TA-1001 device plug / PCIe column, row S19; pp. 14-16 port/detection definitions; p. 12, Table 4-2 S Series Signals, SFF-TA-1001 device plug / PCIe column, row S1; pp. 14-16 port/detection definitions; p. 12, Table 4-2 S Series Signals, SFF-TA-1001 device plug / PCIe column, row S20; pp. 14-16 port/detection definitions; p. 12, Table 4-2 S Series Signals, SFF-TA-1001 device plug / PCIe column, row S21; pp. 14-16 port/detection definitions; p. 12, Table 4-2 S Series Signals, SFF-TA-1001 device plug / PCIe column, row S22; pp. 14-16 port/detection definitions; p. 12, Table 4-2 S Series Signals, SFF-TA-1001 device plug / PCIe column, row S23; pp. 14-16 port/detection definitions; p. 12, Table 4-2 S Series Signals, SFF-TA-1001 device plug / PCIe column, row S24; pp. 14-16 port/detection definitions; p. 12, Table 4-2 S Series Signals, SFF-TA-1001 device plug / PCIe column, row S25; pp. 14-16 port/detection definitions; p. 12, Table 4-2 S Series Signals, SFF-TA-1001 device plug / PCIe column, row S26; pp. 14-16 port/detection definitions; p. 12, Table 4-2 S Series Signals, SFF-TA-1001 device plug / PCIe column, row S27; pp. 14-16 port/detection definitions; p. 12, Table 4-2 S Series Signals, SFF-TA-1001 device plug / PCIe column, row S28; pp. 14-16 port/detection definitions; p. 12, Table 4-2 S Series Signals, SFF-TA-1001 device plug / PCIe column, row S2; pp. 14-16 port/detection definitions; p. 12, Table 4-2 S Series Signals, SFF-TA-1001 device plug / PCIe column, row S3; pp. 14-16 port/detection definitions; p. 12, Table 4-2 S Series Signals, SFF-TA-1001 device plug / PCIe column, row S4; pp. 14-16 port/detection definitions; p. 12, Table 4-2 S Series Signals, SFF-TA-1001 device plug / PCIe column, row S5; pp. 14-16 port/detection definitions; p. 12, Table 4-2 S Series Signals, SFF-TA-1001 device plug / PCIe column, row S6; pp. 14-16 port/detection definitions; p. 12, Table 4-2 S Series Signals, SFF-TA-1001 device plug / PCIe column, row S7; pp. 14-16 port/detection definitions; p. 12, Table 4-2 S Series Signals, SFF-TA-1001 device plug / PCIe column, row S8; pp. 14-16 port/detection definitions; p. 12, Table 4-2 S Series Signals, SFF-TA-1001 device plug / PCIe column, row S9; pp. 14-16 port/detection definitions; p. 13, Table 4-3 E Series Signals, Host receptacle column, row E10; pp. 14-16 port/detection definitions; p. 13, Table 4-3 E Series Signals, Host receptacle column, row E11; pp. 14-16 port/detection definitions; p. 13, Table 4-3 E Series Signals, Host receptacle column, row E12; pp. 14-16 port/detection definitions; p. 13, Table 4-3 E Series Signals, Host receptacle column, row E13; pp. 14-16 port/detection definitions; p. 13, Table 4-3 E Series Signals, Host receptacle column, row E14; pp. 14-16 port/detection definitions; p. 13, Table 4-3 E Series Signals, Host receptacle column, row E15; pp. 14-16 port/detection definitions; p. 13, Table 4-3 E Series Signals, Host receptacle column, row E16; pp. 14-16 port/detection definitions; p. 13, Table 4-3 E Series Signals, Host receptacle column, row E17; pp. 14-16 port/detection definitions; p. 13, Table 4-3 E Series Signals, Host receptacle column, row E18; pp. 14-16 port/detection definitions; p. 13, Table 4-3 E Series Signals, Host receptacle column, row E19; pp. 14-16 port/detection definitions; p. 13, Table 4-3 E Series Signals, Host receptacle column, row E1; pp. 14-16 port/detection definitions; p. 13, Table 4-3 E Series Signals, Host receptacle column, row E20; pp. 14-16 port/detection definitions; p. 13, Table 4-3 E Series Signals, Host receptacle column, row E21; pp. 14-16 port/detection definitions; p. 13, Table 4-3 E Series Signals, Host receptacle column, row E22; pp. 14-16 port/detection definitions; p. 13, Table 4-3 E Series Signals, Host receptacle column, row E23; pp. 14-16 port/detection definitions; p. 13, Table 4-3 E Series Signals, Host receptacle column, row E24; pp. 14-16 port/detection definitions; p. 13, Table 4-3 E Series Signals, Host receptacle column, row E25; pp. 14-16 port/detection definitions; p. 13, Table 4-3 E Series Signals, Host receptacle column, row E2; pp. 14-16 port/detection definitions; p. 13, Table 4-3 E Series Signals, Host receptacle column, row E3; pp. 14-16 port/detection definitions; p. 13, Table 4-3 E Series Signals, Host receptacle column, row E4; pp. 14-16 port/detection definitions; p. 13, Table 4-3 E Series Signals, Host receptacle column, row E5; pp. 14-16 port/detection definitions; p. 13, Table 4-3 E Series Signals, Host receptacle column, row E6; pp. 14-16 port/detection definitions; p. 13, Table 4-3 E Series Signals, Host receptacle column, row E7; pp. 14-16 port/detection definitions; p. 13, Table 4-3 E Series Signals, Host receptacle column, row E8; pp. 14-16 port/detection definitions; p. 13, Table 4-3 E Series Signals, Host receptacle column, row E9; pp. 14-16 port/detection definitions; p. 13, Table 4-3 E Series Signals, SFF-TA-1001 device plug / PCIe column, row E10; pp. 14-16 port/detection definitions; p. 13, Table 4-3 E Series Signals, SFF-TA-1001 device plug / PCIe column, row E11; pp. 14-16 port/detection definitions; p. 13, Table 4-3 E Series Signals, SFF-TA-1001 device plug / PCIe column, row E12; pp. 14-16 port/detection definitions; p. 13, Table 4-3 E Series Signals, SFF-TA-1001 device plug / PCIe column, row E13; pp. 14-16 port/detection definitions; p. 13, Table 4-3 E Series Signals, SFF-TA-1001 device plug / PCIe column, row E14; pp. 14-16 port/detection definitions; p. 13, Table 4-3 E Series Signals, SFF-TA-1001 device plug / PCIe column, row E15; pp. 14-16 port/detection definitions; p. 13, Table 4-3 E Series Signals, SFF-TA-1001 device plug / PCIe column, row E16; pp. 14-16 port/detection definitions; p. 13, Table 4-3 E Series Signals, SFF-TA-1001 device plug / PCIe column, row E17; pp. 14-16 port/detection definitions; p. 13, Table 4-3 E Series Signals, SFF-TA-1001 device plug / PCIe column, row E18; pp. 14-16 port/detection definitions; p. 13, Table 4-3 E Series Signals, SFF-TA-1001 device plug / PCIe column, row E19; pp. 14-16 port/detection definitions; p. 13, Table 4-3 E Series Signals, SFF-TA-1001 device plug / PCIe column, row E1; pp. 14-16 port/detection definitions; p. 13, Table 4-3 E Series Signals, SFF-TA-1001 device plug / PCIe column, row E20; pp. 14-16 port/detection definitions; p. 13, Table 4-3 E Series Signals, SFF-TA-1001 device plug / PCIe column, row E21; pp. 14-16 port/detection definitions; p. 13, Table 4-3 E Series Signals, SFF-TA-1001 device plug / PCIe column, row E22; pp. 14-16 port/detection definitions; p. 13, Table 4-3 E Series Signals, SFF-TA-1001 device plug / PCIe column, row E23; pp. 14-16 port/detection definitions; p. 13, Table 4-3 E Series Signals, SFF-TA-1001 device plug / PCIe column, row E24; pp. 14-16 port/detection definitions; p. 13, Table 4-3 E Series Signals, SFF-TA-1001 device plug / PCIe column, row E25; pp. 14-16 port/detection definitions; p. 13, Table 4-3 E Series Signals, SFF-TA-1001 device plug / PCIe column, row E2; pp. 14-16 port/detection definitions; p. 13, Table 4-3 E Series Signals, SFF-TA-1001 device plug / PCIe column, row E3; pp. 14-16 port/detection definitions; p. 13, Table 4-3 E Series Signals, SFF-TA-1001 device plug / PCIe column, row E4; pp. 14-16 port/detection definitions; p. 13, Table 4-3 E Series Signals, SFF-TA-1001 device plug / PCIe column, row E5; pp. 14-16 port/detection definitions; p. 13, Table 4-3 E Series Signals, SFF-TA-1001 device plug / PCIe column, row E6; pp. 14-16 port/detection definitions; p. 13, Table 4-3 E Series Signals, SFF-TA-1001 device plug / PCIe column, row E7; pp. 14-16 port/detection definitions; p. 13, Table 4-3 E Series Signals, SFF-TA-1001 device plug / PCIe column, row E8; pp. 14-16 port/detection definitions; p. 13, Table 4-3 E Series Signals, SFF-TA-1001 device plug / PCIe column, row E9; pp. 14-16 port/detection definitions; pp.12-13 Tables 4-1 P Series, 4-2 S Series, 4-3 E Series; p.16 Table 4-7 single-port routing; p.13 PET/PER direction notes · Source scope and unresolved evidence are preserved in the engineering variant.

U.2 / Quad PCIe plug — SNIA reference-guide use: original contact normalization. Statuses distinguish comparison agreement, source limits and named-device wiring.

SNIA SFF TWG · SFF-9639: Reference Guide for Multifunction 6X Unshielded Connector Pinouts ↗
p. 7, Table 5-1 P Series Signals (Plug), Quad PCIe column, row P10; p. 7 section 5 reference-guide warning; p. 7, Table 5-1 P Series Signals (Plug), Quad PCIe column, row P11; p. 7 section 5 reference-guide warning; p. 7, Table 5-1 P Series Signals (Plug), Quad PCIe column, row P12; p. 7 section 5 reference-guide warning; p. 7, Table 5-1 P Series Signals (Plug), Quad PCIe column, row P13; p. 7 section 5 reference-guide warning; p. 7, Table 5-1 P Series Signals (Plug), Quad PCIe column, row P14; p. 7 section 5 reference-guide warning; p. 7, Table 5-1 P Series Signals (Plug), Quad PCIe column, row P15; p. 7 section 5 reference-guide warning; p. 7, Table 5-1 P Series Signals (Plug), Quad PCIe column, row P1; p. 7 section 5 reference-guide warning; p. 7, Table 5-1 P Series Signals (Plug), Quad PCIe column, row P2; p. 7 section 5 reference-guide warning; p. 7, Table 5-1 P Series Signals (Plug), Quad PCIe column, row P3; p. 7 section 5 reference-guide warning; p. 7, Table 5-1 P Series Signals (Plug), Quad PCIe column, row P4; p. 7 section 5 reference-guide warning; p. 7, Table 5-1 P Series Signals (Plug), Quad PCIe column, row P5; p. 7 section 5 reference-guide warning; p. 7, Table 5-1 P Series Signals (Plug), Quad PCIe column, row P6; p. 7 section 5 reference-guide warning; p. 7, Table 5-1 P Series Signals (Plug), Quad PCIe column, row P7; p. 7 section 5 reference-guide warning; p. 7, Table 5-1 P Series Signals (Plug), Quad PCIe column, row P8; p. 7 section 5 reference-guide warning; p. 7, Table 5-1 P Series Signals (Plug), Quad PCIe column, row P9; p. 7 section 5 reference-guide warning; p. 8, Table 5-2 S Series Signals (Plug), Quad PCIe column, row S10; p. 7 section 5 reference-guide warning; p. 8, Table 5-2 S Series Signals (Plug), Quad PCIe column, row S11; p. 7 section 5 reference-guide warning; p. 8, Table 5-2 S Series Signals (Plug), Quad PCIe column, row S12; p. 7 section 5 reference-guide warning; p. 8, Table 5-2 S Series Signals (Plug), Quad PCIe column, row S13; p. 7 section 5 reference-guide warning; p. 8, Table 5-2 S Series Signals (Plug), Quad PCIe column, row S14; p. 7 section 5 reference-guide warning; p. 8, Table 5-2 S Series Signals (Plug), Quad PCIe column, row S15; p. 7 section 5 reference-guide warning; p. 8, Table 5-2 S Series Signals (Plug), Quad PCIe column, row S16; p. 7 section 5 reference-guide warning; p. 8, Table 5-2 S Series Signals (Plug), Quad PCIe column, row S17; p. 7 section 5 reference-guide warning; p. 8, Table 5-2 S Series Signals (Plug), Quad PCIe column, row S18; p. 7 section 5 reference-guide warning; p. 8, Table 5-2 S Series Signals (Plug), Quad PCIe column, row S19; p. 7 section 5 reference-guide warning; p. 8, Table 5-2 S Series Signals (Plug), Quad PCIe column, row S1; p. 7 section 5 reference-guide warning; p. 8, Table 5-2 S Series Signals (Plug), Quad PCIe column, row S20; p. 7 section 5 reference-guide warning; p. 8, Table 5-2 S Series Signals (Plug), Quad PCIe column, row S21; p. 7 section 5 reference-guide warning; p. 8, Table 5-2 S Series Signals (Plug), Quad PCIe column, row S22; p. 7 section 5 reference-guide warning; p. 8, Table 5-2 S Series Signals (Plug), Quad PCIe column, row S23; p. 7 section 5 reference-guide warning; p. 8, Table 5-2 S Series Signals (Plug), Quad PCIe column, row S24; p. 7 section 5 reference-guide warning; p. 8, Table 5-2 S Series Signals (Plug), Quad PCIe column, row S25; p. 7 section 5 reference-guide warning; p. 8, Table 5-2 S Series Signals (Plug), Quad PCIe column, row S26; p. 7 section 5 reference-guide warning; p. 8, Table 5-2 S Series Signals (Plug), Quad PCIe column, row S27; p. 7 section 5 reference-guide warning; p. 8, Table 5-2 S Series Signals (Plug), Quad PCIe column, row S28; p. 7 section 5 reference-guide warning; p. 8, Table 5-2 S Series Signals (Plug), Quad PCIe column, row S2; p. 7 section 5 reference-guide warning; p. 8, Table 5-2 S Series Signals (Plug), Quad PCIe column, row S3; p. 7 section 5 reference-guide warning; p. 8, Table 5-2 S Series Signals (Plug), Quad PCIe column, row S4; p. 7 section 5 reference-guide warning; p. 8, Table 5-2 S Series Signals (Plug), Quad PCIe column, row S5; p. 7 section 5 reference-guide warning; p. 8, Table 5-2 S Series Signals (Plug), Quad PCIe column, row S6; p. 7 section 5 reference-guide warning; p. 8, Table 5-2 S Series Signals (Plug), Quad PCIe column, row S7; p. 7 section 5 reference-guide warning; p. 8, Table 5-2 S Series Signals (Plug), Quad PCIe column, row S8; p. 7 section 5 reference-guide warning; p. 8, Table 5-2 S Series Signals (Plug), Quad PCIe column, row S9; p. 7 section 5 reference-guide warning; p. 9, Table 5-3 E Series Signals (Plug), Quad PCIe column, row E10; p. 7 section 5 reference-guide warning; p. 9, Table 5-3 E Series Signals (Plug), Quad PCIe column, row E11; p. 7 section 5 reference-guide warning; p. 9, Table 5-3 E Series Signals (Plug), Quad PCIe column, row E12; p. 7 section 5 reference-guide warning; p. 9, Table 5-3 E Series Signals (Plug), Quad PCIe column, row E13; p. 7 section 5 reference-guide warning; p. 9, Table 5-3 E Series Signals (Plug), Quad PCIe column, row E14; p. 7 section 5 reference-guide warning; p. 9, Table 5-3 E Series Signals (Plug), Quad PCIe column, row E15; p. 7 section 5 reference-guide warning; p. 9, Table 5-3 E Series Signals (Plug), Quad PCIe column, row E16; p. 7 section 5 reference-guide warning; p. 9, Table 5-3 E Series Signals (Plug), Quad PCIe column, row E17; p. 7 section 5 reference-guide warning; p. 9, Table 5-3 E Series Signals (Plug), Quad PCIe column, row E18; p. 7 section 5 reference-guide warning; p. 9, Table 5-3 E Series Signals (Plug), Quad PCIe column, row E19; p. 7 section 5 reference-guide warning; p. 9, Table 5-3 E Series Signals (Plug), Quad PCIe column, row E1; p. 7 section 5 reference-guide warning; p. 9, Table 5-3 E Series Signals (Plug), Quad PCIe column, row E20; p. 7 section 5 reference-guide warning; p. 9, Table 5-3 E Series Signals (Plug), Quad PCIe column, row E21; p. 7 section 5 reference-guide warning; p. 9, Table 5-3 E Series Signals (Plug), Quad PCIe column, row E22; p. 7 section 5 reference-guide warning; p. 9, Table 5-3 E Series Signals (Plug), Quad PCIe column, row E23; p. 7 section 5 reference-guide warning; p. 9, Table 5-3 E Series Signals (Plug), Quad PCIe column, row E24; p. 7 section 5 reference-guide warning; p. 9, Table 5-3 E Series Signals (Plug), Quad PCIe column, row E25; p. 7 section 5 reference-guide warning; p. 9, Table 5-3 E Series Signals (Plug), Quad PCIe column, row E2; p. 7 section 5 reference-guide warning; p. 9, Table 5-3 E Series Signals (Plug), Quad PCIe column, row E3; p. 7 section 5 reference-guide warning; p. 9, Table 5-3 E Series Signals (Plug), Quad PCIe column, row E4; p. 7 section 5 reference-guide warning; p. 9, Table 5-3 E Series Signals (Plug), Quad PCIe column, row E5; p. 7 section 5 reference-guide warning; p. 9, Table 5-3 E Series Signals (Plug), Quad PCIe column, row E6; p. 7 section 5 reference-guide warning; p. 9, Table 5-3 E Series Signals (Plug), Quad PCIe column, row E7; p. 7 section 5 reference-guide warning; p. 9, Table 5-3 E Series Signals (Plug), Quad PCIe column, row E8; p. 7 section 5 reference-guide warning; p. 9, Table 5-3 E Series Signals (Plug), Quad PCIe column, row E9; p. 7 section 5 reference-guide warning; p.8, Table 5-2 PCIe naming note: receiver on device has transmitter signal name · Source scope and unresolved evidence are preserved in the engineering variant.

SNIA SFF TA TWG · SFF-8639: Multifunction 6X Unshielded Connector ↗
p. 22 section 6.1 and Figure 6-1 Contact Numbering Scheme; p. 15 Figure 5-1 Device Free (Plug) Connector · Source scope and unresolved evidence are preserved in the engineering variant.

U.3 / SFF-TA-1001 universal host receptacle: original contact normalization. Statuses distinguish comparison agreement, source limits and named-device wiring.

SNIA SFF TA TWG · SFF-TA-1001: Universal x4 Link Definition for SFF-8639 ↗
p. 12, Table 4-1 P Series Signals, Host receptacle column, row P10; pp. 14-16 port/detection definitions; p. 12, Table 4-1 P Series Signals, Host receptacle column, row P11; pp. 14-16 port/detection definitions; p. 12, Table 4-1 P Series Signals, Host receptacle column, row P12; pp. 14-16 port/detection definitions; p. 12, Table 4-1 P Series Signals, Host receptacle column, row P13; pp. 14-16 port/detection definitions; p. 12, Table 4-1 P Series Signals, Host receptacle column, row P14; pp. 14-16 port/detection definitions; p. 12, Table 4-1 P Series Signals, Host receptacle column, row P15; pp. 14-16 port/detection definitions; p. 12, Table 4-1 P Series Signals, Host receptacle column, row P1; pp. 14-16 port/detection definitions; p. 12, Table 4-1 P Series Signals, Host receptacle column, row P2; pp. 14-16 port/detection definitions; p. 12, Table 4-1 P Series Signals, Host receptacle column, row P3; pp. 14-16 port/detection definitions; p. 12, Table 4-1 P Series Signals, Host receptacle column, row P4; pp. 14-16 port/detection definitions; p. 12, Table 4-1 P Series Signals, Host receptacle column, row P5; pp. 14-16 port/detection definitions; p. 12, Table 4-1 P Series Signals, Host receptacle column, row P6; pp. 14-16 port/detection definitions; p. 12, Table 4-1 P Series Signals, Host receptacle column, row P7; pp. 14-16 port/detection definitions; p. 12, Table 4-1 P Series Signals, Host receptacle column, row P8; pp. 14-16 port/detection definitions; p. 12, Table 4-1 P Series Signals, Host receptacle column, row P9; pp. 14-16 port/detection definitions; p. 12, Table 4-1 P Series Signals, SFF-TA-1001 device plug / PCIe column, row P10; pp. 14-16 port/detection definitions; p. 12, Table 4-1 P Series Signals, SFF-TA-1001 device plug / PCIe column, row P11; pp. 14-16 port/detection definitions; p. 12, Table 4-1 P Series Signals, SFF-TA-1001 device plug / PCIe column, row P12; pp. 14-16 port/detection definitions; p. 12, Table 4-1 P Series Signals, SFF-TA-1001 device plug / PCIe column, row P13; pp. 14-16 port/detection definitions; p. 12, Table 4-1 P Series Signals, SFF-TA-1001 device plug / PCIe column, row P14; pp. 14-16 port/detection definitions; p. 12, Table 4-1 P Series Signals, SFF-TA-1001 device plug / PCIe column, row P15; pp. 14-16 port/detection definitions; p. 12, Table 4-1 P Series Signals, SFF-TA-1001 device plug / PCIe column, row P1; pp. 14-16 port/detection definitions; p. 12, Table 4-1 P Series Signals, SFF-TA-1001 device plug / PCIe column, row P2; pp. 14-16 port/detection definitions; p. 12, Table 4-1 P Series Signals, SFF-TA-1001 device plug / PCIe column, row P3; pp. 14-16 port/detection definitions; p. 12, Table 4-1 P Series Signals, SFF-TA-1001 device plug / PCIe column, row P4; pp. 14-16 port/detection definitions; p. 12, Table 4-1 P Series Signals, SFF-TA-1001 device plug / PCIe column, row P5; pp. 14-16 port/detection definitions; p. 12, Table 4-1 P Series Signals, SFF-TA-1001 device plug / PCIe column, row P6; pp. 14-16 port/detection definitions; p. 12, Table 4-1 P Series Signals, SFF-TA-1001 device plug / PCIe column, row P7; pp. 14-16 port/detection definitions; p. 12, Table 4-1 P Series Signals, SFF-TA-1001 device plug / PCIe column, row P8; pp. 14-16 port/detection definitions; p. 12, Table 4-1 P Series Signals, SFF-TA-1001 device plug / PCIe column, row P9; pp. 14-16 port/detection definitions; p. 12, Table 4-2 S Series Signals, Host receptacle column, row S10; pp. 14-16 port/detection definitions; p. 12, Table 4-2 S Series Signals, Host receptacle column, row S11; pp. 14-16 port/detection definitions; p. 12, Table 4-2 S Series Signals, Host receptacle column, row S12; pp. 14-16 port/detection definitions; p. 12, Table 4-2 S Series Signals, Host receptacle column, row S13; pp. 14-16 port/detection definitions; p. 12, Table 4-2 S Series Signals, Host receptacle column, row S14; pp. 14-16 port/detection definitions; p. 12, Table 4-2 S Series Signals, Host receptacle column, row S15; pp. 14-16 port/detection definitions; p. 12, Table 4-2 S Series Signals, Host receptacle column, row S16; pp. 14-16 port/detection definitions; p. 12, Table 4-2 S Series Signals, Host receptacle column, row S17; pp. 14-16 port/detection definitions; p. 12, Table 4-2 S Series Signals, Host receptacle column, row S18; pp. 14-16 port/detection definitions; p. 12, Table 4-2 S Series Signals, Host receptacle column, row S19; pp. 14-16 port/detection definitions; p. 12, Table 4-2 S Series Signals, Host receptacle column, row S1; pp. 14-16 port/detection definitions; p. 12, Table 4-2 S Series Signals, Host receptacle column, row S20; pp. 14-16 port/detection definitions; p. 12, Table 4-2 S Series Signals, Host receptacle column, row S21; pp. 14-16 port/detection definitions; p. 12, Table 4-2 S Series Signals, Host receptacle column, row S22; pp. 14-16 port/detection definitions; p. 12, Table 4-2 S Series Signals, Host receptacle column, row S23; pp. 14-16 port/detection definitions; p. 12, Table 4-2 S Series Signals, Host receptacle column, row S24; pp. 14-16 port/detection definitions; p. 12, Table 4-2 S Series Signals, Host receptacle column, row S25; pp. 14-16 port/detection definitions; p. 12, Table 4-2 S Series Signals, Host receptacle column, row S26; pp. 14-16 port/detection definitions; p. 12, Table 4-2 S Series Signals, Host receptacle column, row S27; pp. 14-16 port/detection definitions; p. 12, Table 4-2 S Series Signals, Host receptacle column, row S28; pp. 14-16 port/detection definitions; p. 12, Table 4-2 S Series Signals, Host receptacle column, row S2; pp. 14-16 port/detection definitions; p. 12, Table 4-2 S Series Signals, Host receptacle column, row S3; pp. 14-16 port/detection definitions; p. 12, Table 4-2 S Series Signals, Host receptacle column, row S4; pp. 14-16 port/detection definitions; p. 12, Table 4-2 S Series Signals, Host receptacle column, row S5; pp. 14-16 port/detection definitions; p. 12, Table 4-2 S Series Signals, Host receptacle column, row S6; pp. 14-16 port/detection definitions; p. 12, Table 4-2 S Series Signals, Host receptacle column, row S7; pp. 14-16 port/detection definitions; p. 12, Table 4-2 S Series Signals, Host receptacle column, row S8; pp. 14-16 port/detection definitions; p. 12, Table 4-2 S Series Signals, Host receptacle column, row S9; pp. 14-16 port/detection definitions; p. 12, Table 4-2 S Series Signals, SFF-TA-1001 device plug / PCIe column, row S10; pp. 14-16 port/detection definitions; p. 12, Table 4-2 S Series Signals, SFF-TA-1001 device plug / PCIe column, row S11; pp. 14-16 port/detection definitions; p. 12, Table 4-2 S Series Signals, SFF-TA-1001 device plug / PCIe column, row S12; pp. 14-16 port/detection definitions; p. 12, Table 4-2 S Series Signals, SFF-TA-1001 device plug / PCIe column, row S13; pp. 14-16 port/detection definitions; p. 12, Table 4-2 S Series Signals, SFF-TA-1001 device plug / PCIe column, row S14; pp. 14-16 port/detection definitions; p. 12, Table 4-2 S Series Signals, SFF-TA-1001 device plug / PCIe column, row S15; pp. 14-16 port/detection definitions; p. 12, Table 4-2 S Series Signals, SFF-TA-1001 device plug / PCIe column, row S16; pp. 14-16 port/detection definitions; p. 12, Table 4-2 S Series Signals, SFF-TA-1001 device plug / PCIe column, row S17; pp. 14-16 port/detection definitions; p. 12, Table 4-2 S Series Signals, SFF-TA-1001 device plug / PCIe column, row S18; pp. 14-16 port/detection definitions; p. 12, Table 4-2 S Series Signals, SFF-TA-1001 device plug / PCIe column, row S19; pp. 14-16 port/detection definitions; p. 12, Table 4-2 S Series Signals, SFF-TA-1001 device plug / PCIe column, row S1; pp. 14-16 port/detection definitions; p. 12, Table 4-2 S Series Signals, SFF-TA-1001 device plug / PCIe column, row S20; pp. 14-16 port/detection definitions; p. 12, Table 4-2 S Series Signals, SFF-TA-1001 device plug / PCIe column, row S21; pp. 14-16 port/detection definitions; p. 12, Table 4-2 S Series Signals, SFF-TA-1001 device plug / PCIe column, row S22; pp. 14-16 port/detection definitions; p. 12, Table 4-2 S Series Signals, SFF-TA-1001 device plug / PCIe column, row S23; pp. 14-16 port/detection definitions; p. 12, Table 4-2 S Series Signals, SFF-TA-1001 device plug / PCIe column, row S24; pp. 14-16 port/detection definitions; p. 12, Table 4-2 S Series Signals, SFF-TA-1001 device plug / PCIe column, row S25; pp. 14-16 port/detection definitions; p. 12, Table 4-2 S Series Signals, SFF-TA-1001 device plug / PCIe column, row S26; pp. 14-16 port/detection definitions; p. 12, Table 4-2 S Series Signals, SFF-TA-1001 device plug / PCIe column, row S27; pp. 14-16 port/detection definitions; p. 12, Table 4-2 S Series Signals, SFF-TA-1001 device plug / PCIe column, row S28; pp. 14-16 port/detection definitions; p. 12, Table 4-2 S Series Signals, SFF-TA-1001 device plug / PCIe column, row S2; pp. 14-16 port/detection definitions; p. 12, Table 4-2 S Series Signals, SFF-TA-1001 device plug / PCIe column, row S3; pp. 14-16 port/detection definitions; p. 12, Table 4-2 S Series Signals, SFF-TA-1001 device plug / PCIe column, row S4; pp. 14-16 port/detection definitions; p. 12, Table 4-2 S Series Signals, SFF-TA-1001 device plug / PCIe column, row S5; pp. 14-16 port/detection definitions; p. 12, Table 4-2 S Series Signals, SFF-TA-1001 device plug / PCIe column, row S6; pp. 14-16 port/detection definitions; p. 12, Table 4-2 S Series Signals, SFF-TA-1001 device plug / PCIe column, row S7; pp. 14-16 port/detection definitions; p. 12, Table 4-2 S Series Signals, SFF-TA-1001 device plug / PCIe column, row S8; pp. 14-16 port/detection definitions; p. 12, Table 4-2 S Series Signals, SFF-TA-1001 device plug / PCIe column, row S9; pp. 14-16 port/detection definitions; p. 13, Table 4-3 E Series Signals, Host receptacle column, row E10; pp. 14-16 port/detection definitions; p. 13, Table 4-3 E Series Signals, Host receptacle column, row E11; pp. 14-16 port/detection definitions; p. 13, Table 4-3 E Series Signals, Host receptacle column, row E12; pp. 14-16 port/detection definitions; p. 13, Table 4-3 E Series Signals, Host receptacle column, row E13; pp. 14-16 port/detection definitions; p. 13, Table 4-3 E Series Signals, Host receptacle column, row E14; pp. 14-16 port/detection definitions; p. 13, Table 4-3 E Series Signals, Host receptacle column, row E15; pp. 14-16 port/detection definitions; p. 13, Table 4-3 E Series Signals, Host receptacle column, row E16; pp. 14-16 port/detection definitions; p. 13, Table 4-3 E Series Signals, Host receptacle column, row E17; pp. 14-16 port/detection definitions; p. 13, Table 4-3 E Series Signals, Host receptacle column, row E18; pp. 14-16 port/detection definitions; p. 13, Table 4-3 E Series Signals, Host receptacle column, row E19; pp. 14-16 port/detection definitions; p. 13, Table 4-3 E Series Signals, Host receptacle column, row E1; pp. 14-16 port/detection definitions; p. 13, Table 4-3 E Series Signals, Host receptacle column, row E20; pp. 14-16 port/detection definitions; p. 13, Table 4-3 E Series Signals, Host receptacle column, row E21; pp. 14-16 port/detection definitions; p. 13, Table 4-3 E Series Signals, Host receptacle column, row E22; pp. 14-16 port/detection definitions; p. 13, Table 4-3 E Series Signals, Host receptacle column, row E23; pp. 14-16 port/detection definitions; p. 13, Table 4-3 E Series Signals, Host receptacle column, row E24; pp. 14-16 port/detection definitions; p. 13, Table 4-3 E Series Signals, Host receptacle column, row E25; pp. 14-16 port/detection definitions; p. 13, Table 4-3 E Series Signals, Host receptacle column, row E2; pp. 14-16 port/detection definitions; p. 13, Table 4-3 E Series Signals, Host receptacle column, row E3; pp. 14-16 port/detection definitions; p. 13, Table 4-3 E Series Signals, Host receptacle column, row E4; pp. 14-16 port/detection definitions; p. 13, Table 4-3 E Series Signals, Host receptacle column, row E5; pp. 14-16 port/detection definitions; p. 13, Table 4-3 E Series Signals, Host receptacle column, row E6; pp. 14-16 port/detection definitions; p. 13, Table 4-3 E Series Signals, Host receptacle column, row E7; pp. 14-16 port/detection definitions; p. 13, Table 4-3 E Series Signals, Host receptacle column, row E8; pp. 14-16 port/detection definitions; p. 13, Table 4-3 E Series Signals, Host receptacle column, row E9; pp. 14-16 port/detection definitions; p. 13, Table 4-3 E Series Signals, SFF-TA-1001 device plug / PCIe column, row E10; pp. 14-16 port/detection definitions; p. 13, Table 4-3 E Series Signals, SFF-TA-1001 device plug / PCIe column, row E11; pp. 14-16 port/detection definitions; p. 13, Table 4-3 E Series Signals, SFF-TA-1001 device plug / PCIe column, row E12; pp. 14-16 port/detection definitions; p. 13, Table 4-3 E Series Signals, SFF-TA-1001 device plug / PCIe column, row E13; pp. 14-16 port/detection definitions; p. 13, Table 4-3 E Series Signals, SFF-TA-1001 device plug / PCIe column, row E14; pp. 14-16 port/detection definitions; p. 13, Table 4-3 E Series Signals, SFF-TA-1001 device plug / PCIe column, row E15; pp. 14-16 port/detection definitions; p. 13, Table 4-3 E Series Signals, SFF-TA-1001 device plug / PCIe column, row E16; pp. 14-16 port/detection definitions; p. 13, Table 4-3 E Series Signals, SFF-TA-1001 device plug / PCIe column, row E17; pp. 14-16 port/detection definitions; p. 13, Table 4-3 E Series Signals, SFF-TA-1001 device plug / PCIe column, row E18; pp. 14-16 port/detection definitions; p. 13, Table 4-3 E Series Signals, SFF-TA-1001 device plug / PCIe column, row E19; pp. 14-16 port/detection definitions; p. 13, Table 4-3 E Series Signals, SFF-TA-1001 device plug / PCIe column, row E1; pp. 14-16 port/detection definitions; p. 13, Table 4-3 E Series Signals, SFF-TA-1001 device plug / PCIe column, row E20; pp. 14-16 port/detection definitions; p. 13, Table 4-3 E Series Signals, SFF-TA-1001 device plug / PCIe column, row E21; pp. 14-16 port/detection definitions; p. 13, Table 4-3 E Series Signals, SFF-TA-1001 device plug / PCIe column, row E22; pp. 14-16 port/detection definitions; p. 13, Table 4-3 E Series Signals, SFF-TA-1001 device plug / PCIe column, row E23; pp. 14-16 port/detection definitions; p. 13, Table 4-3 E Series Signals, SFF-TA-1001 device plug / PCIe column, row E24; pp. 14-16 port/detection definitions; p. 13, Table 4-3 E Series Signals, SFF-TA-1001 device plug / PCIe column, row E25; pp. 14-16 port/detection definitions; p. 13, Table 4-3 E Series Signals, SFF-TA-1001 device plug / PCIe column, row E2; pp. 14-16 port/detection definitions; p. 13, Table 4-3 E Series Signals, SFF-TA-1001 device plug / PCIe column, row E3; pp. 14-16 port/detection definitions; p. 13, Table 4-3 E Series Signals, SFF-TA-1001 device plug / PCIe column, row E4; pp. 14-16 port/detection definitions; p. 13, Table 4-3 E Series Signals, SFF-TA-1001 device plug / PCIe column, row E5; pp. 14-16 port/detection definitions; p. 13, Table 4-3 E Series Signals, SFF-TA-1001 device plug / PCIe column, row E6; pp. 14-16 port/detection definitions; p. 13, Table 4-3 E Series Signals, SFF-TA-1001 device plug / PCIe column, row E7; pp. 14-16 port/detection definitions; p. 13, Table 4-3 E Series Signals, SFF-TA-1001 device plug / PCIe column, row E8; pp. 14-16 port/detection definitions; p. 13, Table 4-3 E Series Signals, SFF-TA-1001 device plug / PCIe column, row E9; pp. 14-16 port/detection definitions; pp.12-13 Tables 4-1 P Series, 4-2 S Series, 4-3 E Series; p.16 Table 4-7 single-port routing; p.13 PET/PER direction notes · Source scope and unresolved evidence are preserved in the engineering variant.

SNIA SFF TA TWG · SFF-8639: Multifunction 6X Unshielded Connector ↗
p. 22 section 6.1 and Figure 6-1 Contact Numbering Scheme; p. 15 Figure 5-1 Device Free (Plug) Connector · Source scope and unresolved evidence are preserved in the engineering variant.

U.3 / SFF-TA-1001 PCIe device plug: original contact normalization. Statuses distinguish comparison agreement, source limits and named-device wiring.

SNIA SFF TA TWG · SFF-TA-1001: Universal x4 Link Definition for SFF-8639 ↗
p. 12, Table 4-1 P Series Signals, Host receptacle column, row P10; pp. 14-16 port/detection definitions; p. 12, Table 4-1 P Series Signals, Host receptacle column, row P11; pp. 14-16 port/detection definitions; p. 12, Table 4-1 P Series Signals, Host receptacle column, row P12; pp. 14-16 port/detection definitions; p. 12, Table 4-1 P Series Signals, Host receptacle column, row P13; pp. 14-16 port/detection definitions; p. 12, Table 4-1 P Series Signals, Host receptacle column, row P14; pp. 14-16 port/detection definitions; p. 12, Table 4-1 P Series Signals, Host receptacle column, row P15; pp. 14-16 port/detection definitions; p. 12, Table 4-1 P Series Signals, Host receptacle column, row P1; pp. 14-16 port/detection definitions; p. 12, Table 4-1 P Series Signals, Host receptacle column, row P2; pp. 14-16 port/detection definitions; p. 12, Table 4-1 P Series Signals, Host receptacle column, row P3; pp. 14-16 port/detection definitions; p. 12, Table 4-1 P Series Signals, Host receptacle column, row P4; pp. 14-16 port/detection definitions; p. 12, Table 4-1 P Series Signals, Host receptacle column, row P5; pp. 14-16 port/detection definitions; p. 12, Table 4-1 P Series Signals, Host receptacle column, row P6; pp. 14-16 port/detection definitions; p. 12, Table 4-1 P Series Signals, Host receptacle column, row P7; pp. 14-16 port/detection definitions; p. 12, Table 4-1 P Series Signals, Host receptacle column, row P8; pp. 14-16 port/detection definitions; p. 12, Table 4-1 P Series Signals, Host receptacle column, row P9; pp. 14-16 port/detection definitions; p. 12, Table 4-1 P Series Signals, SFF-TA-1001 device plug / PCIe column, row P10; pp. 14-16 port/detection definitions; p. 12, Table 4-1 P Series Signals, SFF-TA-1001 device plug / PCIe column, row P11; pp. 14-16 port/detection definitions; p. 12, Table 4-1 P Series Signals, SFF-TA-1001 device plug / PCIe column, row P12; pp. 14-16 port/detection definitions; p. 12, Table 4-1 P Series Signals, SFF-TA-1001 device plug / PCIe column, row P13; pp. 14-16 port/detection definitions; p. 12, Table 4-1 P Series Signals, SFF-TA-1001 device plug / PCIe column, row P14; pp. 14-16 port/detection definitions; p. 12, Table 4-1 P Series Signals, SFF-TA-1001 device plug / PCIe column, row P15; pp. 14-16 port/detection definitions; p. 12, Table 4-1 P Series Signals, SFF-TA-1001 device plug / PCIe column, row P1; pp. 14-16 port/detection definitions; p. 12, Table 4-1 P Series Signals, SFF-TA-1001 device plug / PCIe column, row P2; pp. 14-16 port/detection definitions; p. 12, Table 4-1 P Series Signals, SFF-TA-1001 device plug / PCIe column, row P3; pp. 14-16 port/detection definitions; p. 12, Table 4-1 P Series Signals, SFF-TA-1001 device plug / PCIe column, row P4; pp. 14-16 port/detection definitions; p. 12, Table 4-1 P Series Signals, SFF-TA-1001 device plug / PCIe column, row P5; pp. 14-16 port/detection definitions; p. 12, Table 4-1 P Series Signals, SFF-TA-1001 device plug / PCIe column, row P6; pp. 14-16 port/detection definitions; p. 12, Table 4-1 P Series Signals, SFF-TA-1001 device plug / PCIe column, row P7; pp. 14-16 port/detection definitions; p. 12, Table 4-1 P Series Signals, SFF-TA-1001 device plug / PCIe column, row P8; pp. 14-16 port/detection definitions; p. 12, Table 4-1 P Series Signals, SFF-TA-1001 device plug / PCIe column, row P9; pp. 14-16 port/detection definitions; p. 12, Table 4-2 S Series Signals, Host receptacle column, row S10; pp. 14-16 port/detection definitions; p. 12, Table 4-2 S Series Signals, Host receptacle column, row S11; pp. 14-16 port/detection definitions; p. 12, Table 4-2 S Series Signals, Host receptacle column, row S12; pp. 14-16 port/detection definitions; p. 12, Table 4-2 S Series Signals, Host receptacle column, row S13; pp. 14-16 port/detection definitions; p. 12, Table 4-2 S Series Signals, Host receptacle column, row S14; pp. 14-16 port/detection definitions; p. 12, Table 4-2 S Series Signals, Host receptacle column, row S15; pp. 14-16 port/detection definitions; p. 12, Table 4-2 S Series Signals, Host receptacle column, row S16; pp. 14-16 port/detection definitions; p. 12, Table 4-2 S Series Signals, Host receptacle column, row S17; pp. 14-16 port/detection definitions; p. 12, Table 4-2 S Series Signals, Host receptacle column, row S18; pp. 14-16 port/detection definitions; p. 12, Table 4-2 S Series Signals, Host receptacle column, row S19; pp. 14-16 port/detection definitions; p. 12, Table 4-2 S Series Signals, Host receptacle column, row S1; pp. 14-16 port/detection definitions; p. 12, Table 4-2 S Series Signals, Host receptacle column, row S20; pp. 14-16 port/detection definitions; p. 12, Table 4-2 S Series Signals, Host receptacle column, row S21; pp. 14-16 port/detection definitions; p. 12, Table 4-2 S Series Signals, Host receptacle column, row S22; pp. 14-16 port/detection definitions; p. 12, Table 4-2 S Series Signals, Host receptacle column, row S23; pp. 14-16 port/detection definitions; p. 12, Table 4-2 S Series Signals, Host receptacle column, row S24; pp. 14-16 port/detection definitions; p. 12, Table 4-2 S Series Signals, Host receptacle column, row S25; pp. 14-16 port/detection definitions; p. 12, Table 4-2 S Series Signals, Host receptacle column, row S26; pp. 14-16 port/detection definitions; p. 12, Table 4-2 S Series Signals, Host receptacle column, row S27; pp. 14-16 port/detection definitions; p. 12, Table 4-2 S Series Signals, Host receptacle column, row S28; pp. 14-16 port/detection definitions; p. 12, Table 4-2 S Series Signals, Host receptacle column, row S2; pp. 14-16 port/detection definitions; p. 12, Table 4-2 S Series Signals, Host receptacle column, row S3; pp. 14-16 port/detection definitions; p. 12, Table 4-2 S Series Signals, Host receptacle column, row S4; pp. 14-16 port/detection definitions; p. 12, Table 4-2 S Series Signals, Host receptacle column, row S5; pp. 14-16 port/detection definitions; p. 12, Table 4-2 S Series Signals, Host receptacle column, row S6; pp. 14-16 port/detection definitions; p. 12, Table 4-2 S Series Signals, Host receptacle column, row S7; pp. 14-16 port/detection definitions; p. 12, Table 4-2 S Series Signals, Host receptacle column, row S8; pp. 14-16 port/detection definitions; p. 12, Table 4-2 S Series Signals, Host receptacle column, row S9; pp. 14-16 port/detection definitions; p. 12, Table 4-2 S Series Signals, SFF-TA-1001 device plug / PCIe column, row S10; pp. 14-16 port/detection definitions; p. 12, Table 4-2 S Series Signals, SFF-TA-1001 device plug / PCIe column, row S11; pp. 14-16 port/detection definitions; p. 12, Table 4-2 S Series Signals, SFF-TA-1001 device plug / PCIe column, row S12; pp. 14-16 port/detection definitions; p. 12, Table 4-2 S Series Signals, SFF-TA-1001 device plug / PCIe column, row S13; pp. 14-16 port/detection definitions; p. 12, Table 4-2 S Series Signals, SFF-TA-1001 device plug / PCIe column, row S14; pp. 14-16 port/detection definitions; p. 12, Table 4-2 S Series Signals, SFF-TA-1001 device plug / PCIe column, row S15; pp. 14-16 port/detection definitions; p. 12, Table 4-2 S Series Signals, SFF-TA-1001 device plug / PCIe column, row S16; pp. 14-16 port/detection definitions; p. 12, Table 4-2 S Series Signals, SFF-TA-1001 device plug / PCIe column, row S17; pp. 14-16 port/detection definitions; p. 12, Table 4-2 S Series Signals, SFF-TA-1001 device plug / PCIe column, row S18; pp. 14-16 port/detection definitions; p. 12, Table 4-2 S Series Signals, SFF-TA-1001 device plug / PCIe column, row S19; pp. 14-16 port/detection definitions; p. 12, Table 4-2 S Series Signals, SFF-TA-1001 device plug / PCIe column, row S1; pp. 14-16 port/detection definitions; p. 12, Table 4-2 S Series Signals, SFF-TA-1001 device plug / PCIe column, row S20; pp. 14-16 port/detection definitions; p. 12, Table 4-2 S Series Signals, SFF-TA-1001 device plug / PCIe column, row S21; pp. 14-16 port/detection definitions; p. 12, Table 4-2 S Series Signals, SFF-TA-1001 device plug / PCIe column, row S22; pp. 14-16 port/detection definitions; p. 12, Table 4-2 S Series Signals, SFF-TA-1001 device plug / PCIe column, row S23; pp. 14-16 port/detection definitions; p. 12, Table 4-2 S Series Signals, SFF-TA-1001 device plug / PCIe column, row S24; pp. 14-16 port/detection definitions; p. 12, Table 4-2 S Series Signals, SFF-TA-1001 device plug / PCIe column, row S25; pp. 14-16 port/detection definitions; p. 12, Table 4-2 S Series Signals, SFF-TA-1001 device plug / PCIe column, row S26; pp. 14-16 port/detection definitions; p. 12, Table 4-2 S Series Signals, SFF-TA-1001 device plug / PCIe column, row S27; pp. 14-16 port/detection definitions; p. 12, Table 4-2 S Series Signals, SFF-TA-1001 device plug / PCIe column, row S28; pp. 14-16 port/detection definitions; p. 12, Table 4-2 S Series Signals, SFF-TA-1001 device plug / PCIe column, row S2; pp. 14-16 port/detection definitions; p. 12, Table 4-2 S Series Signals, SFF-TA-1001 device plug / PCIe column, row S3; pp. 14-16 port/detection definitions; p. 12, Table 4-2 S Series Signals, SFF-TA-1001 device plug / PCIe column, row S4; pp. 14-16 port/detection definitions; p. 12, Table 4-2 S Series Signals, SFF-TA-1001 device plug / PCIe column, row S5; pp. 14-16 port/detection definitions; p. 12, Table 4-2 S Series Signals, SFF-TA-1001 device plug / PCIe column, row S6; pp. 14-16 port/detection definitions; p. 12, Table 4-2 S Series Signals, SFF-TA-1001 device plug / PCIe column, row S7; pp. 14-16 port/detection definitions; p. 12, Table 4-2 S Series Signals, SFF-TA-1001 device plug / PCIe column, row S8; pp. 14-16 port/detection definitions; p. 12, Table 4-2 S Series Signals, SFF-TA-1001 device plug / PCIe column, row S9; pp. 14-16 port/detection definitions; p. 13, Table 4-3 E Series Signals, Host receptacle column, row E10; pp. 14-16 port/detection definitions; p. 13, Table 4-3 E Series Signals, Host receptacle column, row E11; pp. 14-16 port/detection definitions; p. 13, Table 4-3 E Series Signals, Host receptacle column, row E12; pp. 14-16 port/detection definitions; p. 13, Table 4-3 E Series Signals, Host receptacle column, row E13; pp. 14-16 port/detection definitions; p. 13, Table 4-3 E Series Signals, Host receptacle column, row E14; pp. 14-16 port/detection definitions; p. 13, Table 4-3 E Series Signals, Host receptacle column, row E15; pp. 14-16 port/detection definitions; p. 13, Table 4-3 E Series Signals, Host receptacle column, row E16; pp. 14-16 port/detection definitions; p. 13, Table 4-3 E Series Signals, Host receptacle column, row E17; pp. 14-16 port/detection definitions; p. 13, Table 4-3 E Series Signals, Host receptacle column, row E18; pp. 14-16 port/detection definitions; p. 13, Table 4-3 E Series Signals, Host receptacle column, row E19; pp. 14-16 port/detection definitions; p. 13, Table 4-3 E Series Signals, Host receptacle column, row E1; pp. 14-16 port/detection definitions; p. 13, Table 4-3 E Series Signals, Host receptacle column, row E20; pp. 14-16 port/detection definitions; p. 13, Table 4-3 E Series Signals, Host receptacle column, row E21; pp. 14-16 port/detection definitions; p. 13, Table 4-3 E Series Signals, Host receptacle column, row E22; pp. 14-16 port/detection definitions; p. 13, Table 4-3 E Series Signals, Host receptacle column, row E23; pp. 14-16 port/detection definitions; p. 13, Table 4-3 E Series Signals, Host receptacle column, row E24; pp. 14-16 port/detection definitions; p. 13, Table 4-3 E Series Signals, Host receptacle column, row E25; pp. 14-16 port/detection definitions; p. 13, Table 4-3 E Series Signals, Host receptacle column, row E2; pp. 14-16 port/detection definitions; p. 13, Table 4-3 E Series Signals, Host receptacle column, row E3; pp. 14-16 port/detection definitions; p. 13, Table 4-3 E Series Signals, Host receptacle column, row E4; pp. 14-16 port/detection definitions; p. 13, Table 4-3 E Series Signals, Host receptacle column, row E5; pp. 14-16 port/detection definitions; p. 13, Table 4-3 E Series Signals, Host receptacle column, row E6; pp. 14-16 port/detection definitions; p. 13, Table 4-3 E Series Signals, Host receptacle column, row E7; pp. 14-16 port/detection definitions; p. 13, Table 4-3 E Series Signals, Host receptacle column, row E8; pp. 14-16 port/detection definitions; p. 13, Table 4-3 E Series Signals, Host receptacle column, row E9; pp. 14-16 port/detection definitions; p. 13, Table 4-3 E Series Signals, SFF-TA-1001 device plug / PCIe column, row E10; pp. 14-16 port/detection definitions; p. 13, Table 4-3 E Series Signals, SFF-TA-1001 device plug / PCIe column, row E11; pp. 14-16 port/detection definitions; p. 13, Table 4-3 E Series Signals, SFF-TA-1001 device plug / PCIe column, row E12; pp. 14-16 port/detection definitions; p. 13, Table 4-3 E Series Signals, SFF-TA-1001 device plug / PCIe column, row E13; pp. 14-16 port/detection definitions; p. 13, Table 4-3 E Series Signals, SFF-TA-1001 device plug / PCIe column, row E14; pp. 14-16 port/detection definitions; p. 13, Table 4-3 E Series Signals, SFF-TA-1001 device plug / PCIe column, row E15; pp. 14-16 port/detection definitions; p. 13, Table 4-3 E Series Signals, SFF-TA-1001 device plug / PCIe column, row E16; pp. 14-16 port/detection definitions; p. 13, Table 4-3 E Series Signals, SFF-TA-1001 device plug / PCIe column, row E17; pp. 14-16 port/detection definitions; p. 13, Table 4-3 E Series Signals, SFF-TA-1001 device plug / PCIe column, row E18; pp. 14-16 port/detection definitions; p. 13, Table 4-3 E Series Signals, SFF-TA-1001 device plug / PCIe column, row E19; pp. 14-16 port/detection definitions; p. 13, Table 4-3 E Series Signals, SFF-TA-1001 device plug / PCIe column, row E1; pp. 14-16 port/detection definitions; p. 13, Table 4-3 E Series Signals, SFF-TA-1001 device plug / PCIe column, row E20; pp. 14-16 port/detection definitions; p. 13, Table 4-3 E Series Signals, SFF-TA-1001 device plug / PCIe column, row E21; pp. 14-16 port/detection definitions; p. 13, Table 4-3 E Series Signals, SFF-TA-1001 device plug / PCIe column, row E22; pp. 14-16 port/detection definitions; p. 13, Table 4-3 E Series Signals, SFF-TA-1001 device plug / PCIe column, row E23; pp. 14-16 port/detection definitions; p. 13, Table 4-3 E Series Signals, SFF-TA-1001 device plug / PCIe column, row E24; pp. 14-16 port/detection definitions; p. 13, Table 4-3 E Series Signals, SFF-TA-1001 device plug / PCIe column, row E25; pp. 14-16 port/detection definitions; p. 13, Table 4-3 E Series Signals, SFF-TA-1001 device plug / PCIe column, row E2; pp. 14-16 port/detection definitions; p. 13, Table 4-3 E Series Signals, SFF-TA-1001 device plug / PCIe column, row E3; pp. 14-16 port/detection definitions; p. 13, Table 4-3 E Series Signals, SFF-TA-1001 device plug / PCIe column, row E4; pp. 14-16 port/detection definitions; p. 13, Table 4-3 E Series Signals, SFF-TA-1001 device plug / PCIe column, row E5; pp. 14-16 port/detection definitions; p. 13, Table 4-3 E Series Signals, SFF-TA-1001 device plug / PCIe column, row E6; pp. 14-16 port/detection definitions; p. 13, Table 4-3 E Series Signals, SFF-TA-1001 device plug / PCIe column, row E7; pp. 14-16 port/detection definitions; p. 13, Table 4-3 E Series Signals, SFF-TA-1001 device plug / PCIe column, row E8; pp. 14-16 port/detection definitions; p. 13, Table 4-3 E Series Signals, SFF-TA-1001 device plug / PCIe column, row E9; pp. 14-16 port/detection definitions; pp.12-13 Tables 4-1 P Series, 4-2 S Series, 4-3 E Series; p.16 Table 4-7 single-port routing; p.13 PET/PER direction notes · Source scope and unresolved evidence are preserved in the engineering variant.

SNIA SFF TA TWG · SFF-8639: Multifunction 6X Unshielded Connector ↗
p. 22 section 6.1 and Figure 6-1 Contact Numbering Scheme; p. 15 Figure 5-1 Device Free (Plug) Connector · Source scope and unresolved evidence are preserved in the engineering variant.

Seagate Nytro 5060 2.5-inch U.2 device (named model family): original contact normalization. Statuses distinguish comparison agreement, source limits and named-device wiring.

SNIA SFF TA TWG · SFF-8639: Multifunction 6X Unshielded Connector ↗
p. 22 section 6.1 and Figure 6-1 Contact Numbering Scheme; p. 15 Figure 5-1 Device Free (Plug) Connector · Source scope and unresolved evidence are preserved in the engineering variant.

Seagate Technology LLC · Nytro 5060 NVMe 2.5-inch SSD Product Manual ↗
p. 52, section 9.5.5 Table 23 Connector SFF-8639 Pin Assignment and Descriptions, row P1; p. 52, section 9.5.5 Table 23 Connector SFF-8639 Pin Assignment and Descriptions, row P10; p. 52, section 9.5.5 Table 23 Connector SFF-8639 Pin Assignment and Descriptions, row P11; p. 52, section 9.5.5 Table 23 Connector SFF-8639 Pin Assignment and Descriptions, row P12; p. 52, section 9.5.5 Table 23 Connector SFF-8639 Pin Assignment and Descriptions, row P13; p. 52, section 9.5.5 Table 23 Connector SFF-8639 Pin Assignment and Descriptions, row P14; p. 52, section 9.5.5 Table 23 Connector SFF-8639 Pin Assignment and Descriptions, row P15; p. 52, section 9.5.5 Table 23 Connector SFF-8639 Pin Assignment and Descriptions, row P2; p. 52, section 9.5.5 Table 23 Connector SFF-8639 Pin Assignment and Descriptions, row P3; p. 52, section 9.5.5 Table 23 Connector SFF-8639 Pin Assignment and Descriptions, row P4; p. 52, section 9.5.5 Table 23 Connector SFF-8639 Pin Assignment and Descriptions, row P5; p. 52, section 9.5.5 Table 23 Connector SFF-8639 Pin Assignment and Descriptions, row P6; p. 52, section 9.5.5 Table 23 Connector SFF-8639 Pin Assignment and Descriptions, row P7; p. 52, section 9.5.5 Table 23 Connector SFF-8639 Pin Assignment and Descriptions, row P8; p. 52, section 9.5.5 Table 23 Connector SFF-8639 Pin Assignment and Descriptions, row P9; p. 52, section 9.5.5 Table 23 Connector SFF-8639 Pin Assignment and Descriptions, row S1; p. 52, section 9.5.5 Table 23 Connector SFF-8639 Pin Assignment and Descriptions, row S10; p. 52, section 9.5.5 Table 23 Connector SFF-8639 Pin Assignment and Descriptions, row S11; p. 52, section 9.5.5 Table 23 Connector SFF-8639 Pin Assignment and Descriptions, row S12; p. 52, section 9.5.5 Table 23 Connector SFF-8639 Pin Assignment and Descriptions, row S13; p. 52, section 9.5.5 Table 23 Connector SFF-8639 Pin Assignment and Descriptions, row S14; p. 52, section 9.5.5 Table 23 Connector SFF-8639 Pin Assignment and Descriptions, row S15; p. 52, section 9.5.5 Table 23 Connector SFF-8639 Pin Assignment and Descriptions, row S16; p. 52, section 9.5.5 Table 23 Connector SFF-8639 Pin Assignment and Descriptions, row S17; p. 52, section 9.5.5 Table 23 Connector SFF-8639 Pin Assignment and Descriptions, row S18; p. 52, section 9.5.5 Table 23 Connector SFF-8639 Pin Assignment and Descriptions, row S19; p. 52, section 9.5.5 Table 23 Connector SFF-8639 Pin Assignment and Descriptions, row S2; p. 52, section 9.5.5 Table 23 Connector SFF-8639 Pin Assignment and Descriptions, row S20; p. 52, section 9.5.5 Table 23 Connector SFF-8639 Pin Assignment and Descriptions, row S3; p. 52, section 9.5.5 Table 23 Connector SFF-8639 Pin Assignment and Descriptions, row S4; p. 52, section 9.5.5 Table 23 Connector SFF-8639 Pin Assignment and Descriptions, row S5; p. 52, section 9.5.5 Table 23 Connector SFF-8639 Pin Assignment and Descriptions, row S6; p. 52, section 9.5.5 Table 23 Connector SFF-8639 Pin Assignment and Descriptions, row S7; p. 52, section 9.5.5 Table 23 Connector SFF-8639 Pin Assignment and Descriptions, row S8; p. 52, section 9.5.5 Table 23 Connector SFF-8639 Pin Assignment and Descriptions, row S9; p. 53, section 9.5.5 Table 23 Connector SFF-8639 Pin Assignment and Descriptions, row E1; p. 53, section 9.5.5 Table 23 Connector SFF-8639 Pin Assignment and Descriptions, row E10; p. 53, section 9.5.5 Table 23 Connector SFF-8639 Pin Assignment and Descriptions, row E11; p. 53, section 9.5.5 Table 23 Connector SFF-8639 Pin Assignment and Descriptions, row E12; p. 53, section 9.5.5 Table 23 Connector SFF-8639 Pin Assignment and Descriptions, row E13; p. 53, section 9.5.5 Table 23 Connector SFF-8639 Pin Assignment and Descriptions, row E14; p. 53, section 9.5.5 Table 23 Connector SFF-8639 Pin Assignment and Descriptions, row E15; p. 53, section 9.5.5 Table 23 Connector SFF-8639 Pin Assignment and Descriptions, row E16; p. 53, section 9.5.5 Table 23 Connector SFF-8639 Pin Assignment and Descriptions, row E17; p. 53, section 9.5.5 Table 23 Connector SFF-8639 Pin Assignment and Descriptions, row E18; p. 53, section 9.5.5 Table 23 Connector SFF-8639 Pin Assignment and Descriptions, row E19; p. 53, section 9.5.5 Table 23 Connector SFF-8639 Pin Assignment and Descriptions, row E2; p. 53, section 9.5.5 Table 23 Connector SFF-8639 Pin Assignment and Descriptions, row E20; p. 53, section 9.5.5 Table 23 Connector SFF-8639 Pin Assignment and Descriptions, row E21; p. 53, section 9.5.5 Table 23 Connector SFF-8639 Pin Assignment and Descriptions, row E22; p. 53, section 9.5.5 Table 23 Connector SFF-8639 Pin Assignment and Descriptions, row E23; p. 53, section 9.5.5 Table 23 Connector SFF-8639 Pin Assignment and Descriptions, row E24; p. 53, section 9.5.5 Table 23 Connector SFF-8639 Pin Assignment and Descriptions, row E25; p. 53, section 9.5.5 Table 23 Connector SFF-8639 Pin Assignment and Descriptions, row E3; p. 53, section 9.5.5 Table 23 Connector SFF-8639 Pin Assignment and Descriptions, row E4; p. 53, section 9.5.5 Table 23 Connector SFF-8639 Pin Assignment and Descriptions, row E5; p. 53, section 9.5.5 Table 23 Connector SFF-8639 Pin Assignment and Descriptions, row E6; p. 53, section 9.5.5 Table 23 Connector SFF-8639 Pin Assignment and Descriptions, row E7; p. 53, section 9.5.5 Table 23 Connector SFF-8639 Pin Assignment and Descriptions, row E8; p. 53, section 9.5.5 Table 23 Connector SFF-8639 Pin Assignment and Descriptions, row E9; p. 53, section 9.5.5 Table 23 Connector SFF-8639 Pin Assignment and Descriptions, row S21; p. 53, section 9.5.5 Table 23 Connector SFF-8639 Pin Assignment and Descriptions, row S22; p. 53, section 9.5.5 Table 23 Connector SFF-8639 Pin Assignment and Descriptions, row S23; p. 53, section 9.5.5 Table 23 Connector SFF-8639 Pin Assignment and Descriptions, row S24; p. 53, section 9.5.5 Table 23 Connector SFF-8639 Pin Assignment and Descriptions, row S25; p. 53, section 9.5.5 Table 23 Connector SFF-8639 Pin Assignment and Descriptions, row S26; p. 53, section 9.5.5 Table 23 Connector SFF-8639 Pin Assignment and Descriptions, row S27; p. 53, section 9.5.5 Table 23 Connector SFF-8639 Pin Assignment and Descriptions, row S28 · Source scope and unresolved evidence are preserved in the engineering variant.