Logical table numbering from Intel Table 5-5; V37 does not convert the table into a physical face-view locator.
Source-scoped identification facts
Each value retains its exact example, role and measurement axis. Facts from different parts must not be combined into an invented component.
Documented examples; not a mating drawing or compatibility approval
Nominal contacts
8S199Documented position count only; no V36 electrical pin map.
Positions / cavity span
8 (Claim C192C)S474Recorded source-scoped values; named examples do not describe every family variant or establish compatibility. Do not infer cable role solely from the equipment category or position count.
Contact rows
2 (Source-described array; C192A); 2 (Source-described array; C192B); 2 (Source-described array; C192E)S199 · S216 · S561Recorded source-scoped values; named examples do not describe every family variant or establish compatibility. V36 catalogue-expansion identification fact only; not independent technical approval, fabrication data, wiring instruction or end-to-end compatibility proof. V37 engineering-depth sidecar fact; source-checked but not independently human-approved, not a fabrication drawing, and not a safe-substitution or repair instruction. Printed page 59 only. The guide-specific connection description is not a PSU-side socket assignment or permission to reuse an unknown cable.
Contact pitch
4.2 mm manufacturer-reported centerline or mating-interface pitch (NVIDIA GRID K2 eight-pin PCIe power header)S765Separate exact examples; retain each value’s source, role, axis and part scope. Exact named example NVIDIA GRID K2 eight-pin PCIe power header: Device-specific board header. Exact example only; no universal geometry, electrical compatibility, fabrication approval or wiring instruction. Named2013board example only. Do not treat as every modernGPUheader geometry or modularPSU pinout.
Dimensions / axis
18 ± 0.25 mm housing width (NVIDIA GRID K2 eight-pin PCIe power header); 11.4 ± 0.25 mm housing height (NVIDIA GRID K2 eight-pin PCIe power header); 18.1 ± 0.25 mm front-to-rear overall connector extent including formed PCB tails (NVIDIA GRID K2 eight-pin PCIe power header)S765Separate exact examples; retain each value’s source, role, axis and part scope. Exact named example NVIDIA GRID K2 eight-pin PCIe power header: Device-specific board header. Exact example only; no universal geometry, electrical compatibility, fabrication approval or wiring instruction. Named2013board example only. Do not treat as every modernGPUheader geometry or modularPSU pinout.
Connector role
plug; headerS199 · S216Recorded source-scoped values; named examples do not describe every family variant or establish compatibility. PCIe auxiliary-power cable plug / add-in-card header interface
Mounting
board (Claim C192E)S561Recorded source-scoped values; named examples do not describe every family variant or establish compatibility. Printed page 59 only. The guide-specific connection description is not a PSU-side socket assignment or permission to reuse an unknown cable.
Keying / polarization
position1indicator and alignment rib shown in Figure7 (NVIDIA GRID K2 eight-pin PCIe power header)S765Separate exact examples; retain each value’s source, role, axis and part scope. Exact named example NVIDIA GRID K2 eight-pin PCIe power header: Device-specific board header. Exact example only; no universal geometry, electrical compatibility, fabrication approval or wiring instruction. Named2013board example only. Do not treat as every modernGPUheader geometry or modularPSU pinout.
Exact part / implementation
NVIDIA GRID K2 eight-pin PCIe power header (NVIDIA GRID K2 eight-pin PCIe power header)S765Separate exact examples; retain each value’s source, role, axis and part scope. Exact named example NVIDIA GRID K2 eight-pin PCIe power header: Device-specific board header. Exact example only; no universal geometry, electrical compatibility, fabrication approval or wiring instruction. Named2013board example only. Do not treat as every modernGPUheader geometry or modularPSU pinout.
View convention
Figure7 front/side/section views of board header; position1indicator and alignment rib explicit; not cable wire-entry map (NVIDIA GRID K2 eight-pin PCIe power header)S765Separate exact examples; retain each value’s source, role, axis and part scope. Exact named example NVIDIA GRID K2 eight-pin PCIe power header: Device-specific board header. Exact example only; no universal geometry, electrical compatibility, fabrication approval or wiring instruction. Named2013board example only. Do not treat as every modernGPUheader geometry or modularPSU pinout.
Not recorded: Populated contacts, Contact gender / arrangement, Coupling / latch, Shell / form, Manufacturer, Series, Recorded markings. Unknown fields stay unknown; illustrations supply no measurements or pin assignments.
Recorded variant and source limits
No mating-face orientation or key geometry is inferred from the assignment table.
The 2x4 add-in-card header may accept a documented 2x3 plug in the Intel design context; this does not authorize arbitrary cable substitutions.
Modular PSU-side pinouts are outside this profile.
GIGABYTE GP-UD850GM-A PG5 modular PCIe 6+2 cable, VGA (card) end: Drawing on the cited page.
Intel rev 2.1a PCIe 2x4, 150 W: Numbered assignments only. The retrieved Intel section supplies a table but no numbered mating-face or wire-side drawing; spatial orientation is UNVERIFIED. Do not mirror these numbers onto an unidentified cable end.
NVIDIA GRID K2 eight-pin auxiliary connector: NVIDIA Figure 7 board-header drawing and its POSITION #1 INDICATOR; Table 3 supplies the numbered signals. Cable rear view is not established.
Intel documents a 2x4 PCIe add-in-card auxiliary-power connector form in the cited ATX design guide.
Intel · ATX Version 3.0 — PCI Express add-in card connectors ↗ PCIe auxiliary power connector section · Identification/reference scope only. V36 does not convert this source into a universal pinout, fabrication drawing, electrical approval or end-to-end compatibility verdict.
C192Bsource checked
Intel ATX Version 3.0 Table 5-5 assigns the PCIe 2x4 auxiliary connector as pins 1–3 +12V3/V4, pin 4 Sense1, pin 5 COM, pin 6 Sense0, and pins 7–8 COM.
Intel · ATX Version 3.0 — PCIe auxiliary power connector assignments ↗ Tables 5-4, 5-5 and 5-7; 12VHPWR connector description · Exact ATX 3.0 design-guide scope only. 12VHPWR is retained as the documented historical form and must not be silently generalized to later 12V-2x6 revisions or proprietary modular-PSU connectors.
Page scope: Original V37 logical-assignment schematic; not to scale and not a mating-face or manufacturing drawing.
Assessment 2026-10-22 · earliest scheduled source review 2027-01-03. This is a recorded-date assessment, not a live source check. Page-level independent review is not established by this panel.
Scoped support: Identifies legacy 2x3 and 2x4 PCIe auxiliary-power forms and the 12VHPWR form with twelve larger power contacts plus four smaller sideband contacts.
Not established / limitations: Identification/reference scope only. V36 does not convert this source into a universal pinout, fabrication drawing, electrical approval or end-to-end compatibility verdict.
Scoped support: Engineering-sidecar source for legacy PCIe 2x3/2x4 assignments and the ATX 3.0 12VHPWR 12+4 assignment/3.0 mm power-contact spacing context.
Not established / limitations: Exact ATX 3.0 design-guide scope only. 12VHPWR is retained as the documented historical form and must not be silently generalized to later 12V-2x6 revisions or proprietary modular-PSU connectors.
Locator: Tables 5-4, 5-5 and 5-7; 12VHPWR connector description
Intel ATX Version 3.0 Table 5-5 assigns the PCIe 2x4 auxiliary connector as pins 1–3 +12V3/V4, pin 4 Sense1, pin 5 COM, pin 6 Sense0, and pins 7–8 COM.
Claim scope: V37 engineering-depth sidecar fact; source-checked but not independently human-approved, not a fabrication drawing, and not a safe-substitution or repair instruction.
Recorded evidence only. An inspection date, publisher label, source link or generated packet is not independent technical review, hardware testing, fabrication approval or a compatibility verdict.