E327 · Source-scoped pinout variants

eSATA 7-pin data connector engineering reference

Named wiring from the pinout research; connector shape alone does not establish capabilities.

Open field note Source trail

Source checked · no independent review claimed · Fabrication approved: no

eSATA 7-pin data connector engineering reference original orientation schematic — Original pinout diagram; read the exact variant and view below. Not to scale.

Contact count

Not asserted

Source-scoped connector interface

Mating boundary

Shape is not the verdict.

Check the exact device and mating connector.

Orientation

How to read this profile

Read the exact variant view convention. Schematic layouts do not establish physical positions.

Source-scoped identification facts

Each value retains its exact example, role and measurement axis. Facts from different parts must not be combined into an invented component.

Documented examples; not a mating drawing or compatibility approval
Nominal contacts	7S094Nominal contact count; some implementations may omit populated positions. It is not a wiring map.
Connector role	plug (ESATA3)S637Named source examples retain separate role, part, view and axis limits; values are not a universal family specification. ESATA3. Documented role: plug. Productwidth15mm andheight9mm describe assembly without endpoint-specific view,so not counted as connector dimensions.; Currenttable temperature20to80C andstorage23to25C appear unusual; no thermal generalization adopted.; Cable length andpackaging sizes excluded from geometry; pitch/rows still not established.
Manufacturer	StarTech.com (ESATA3)S637Named source examples retain separate role, part, view and axis limits; values are not a universal family specification. ESATA3. Documented role: plug. Productwidth15mm andheight9mm describe assembly without endpoint-specific view,so not counted as connector dimensions.; Currenttable temperature20to80C andstorage23to25C appear unusual; no thermal generalization adopted.; Cable length andpackaging sizes excluded from geometry; pitch/rows still not established.
Series	External eSATA cable (ESATA3)S637Named source examples retain separate role, part, view and axis limits; values are not a universal family specification. ESATA3. Documented role: plug. Productwidth15mm andheight9mm describe assembly without endpoint-specific view,so not counted as connector dimensions.; Currenttable temperature20to80C andstorage23to25C appear unusual; no thermal generalization adopted.; Cable length andpackaging sizes excluded from geometry; pitch/rows still not established.
Exact part / implementation	ESATA3 (ESATA3)S637Named source examples retain separate role, part, view and axis limits; values are not a universal family specification. ESATA3. Documented role: plug. Productwidth15mm andheight9mm describe assembly without endpoint-specific view,so not counted as connector dimensions.; Currenttable temperature20to80C andstorage23to25C appear unusual; no thermal generalization adopted.; Cable length andpackaging sizes excluded from geometry; pitch/rows still not established.

Not recorded: Positions / cavity span, Populated contacts, Contact rows, Contact pitch, Dimensions / axis, Contact gender / arrangement, Mounting, Coupling / latch, Keying / polarization, Shell / form, Recorded markings, View convention. Unknown fields stay unknown; illustrations supply no measurements or pin assignments.

Recorded variant and source limits

Check the exact device manual before wiring or applying power.
SATA-IO external single-lane connector (historical draft assignment): Draft v0.108 p.148 §6.5.1 refers to Table 4 p.80. Neutral pair A/B names are retained. Rows 1-7 correspond to the S1-S7 signal segment. ARK-3440 Fig.2.8 shows a host mating face with 7 left, 1 right, but no signal table.
eSATA host plug: Numbered external plug contacts; Figure 94 is the RA SMT plug, Figure 95 a distinct reversed-pinout implementation. No universal board-tail mirror is claimed.
eSATA device plug: Numbered external plug contacts; Figure 94 is the RA SMT plug, Figure 95 a distinct reversed-pinout implementation. No universal board-tail mirror is claimed.

Report a correction to these facts →

Pins & wiring

Pinout

Choose the exact wiring. Pin numbers follow its stated view; a schematic does not establish physical positions. Check your exact device before wiring.

Dark pinout view

What the status labels mean

Confirmed: Recorded research passes agree within this variant; this is not independent human review or hardware validation.
Single source: Only one underlying document, or one pass, supports this assignment.
Device-specific: Supported for the named equipment or wiring only. Check your device’s manual.
Unverified: Missing or conflicting evidence. Do not wire from this row.
Not connected: The source explicitly says NC, no contact or no pin for this wiring.

Wiring variantSATA-IO external single-lane connector (historical draft assignment)

SATA-IO external single-lane connector (historical draft assignment)

View and evidence limits

Draft v0.108 p.148 §6.5.1 refers to Table 4 p.80. Neutral pair A/B names are retained. Rows 1-7 correspond to the S1-S7 signal segment. ARK-3440 Fig.2.8 shows a host mating face with 7 left, 1 right, but no signal table.

P118 eSATA — **Agree**: ground on S1/S4/S7, A+/A- on S2/S3, B-/B+ on S5/S6 — A uses an explicitly identified historical SATA-IO draft plus an Advantech face drawing. B retrieved public **SATA 3.0 Gold, June 2009**, including host/device assignments and separate physical implementations. That fills A's missing final-edition evidence for the historical interface. Same standards issuer and related editions, not independent issuers; no current-edition compliance or powered-eSATA map is claimed.
Documented in an official historical draft; not claimed as a current final standard. No universal TX/RX direction assigned to pair A/B.
Final licensed SATA specification was not obtained. ARK-3440 p.10 establishes the external face but omits signal assignments. Current final compliance and host/device TX/RX expansion remain unverified; eSATAp additional contacts are excluded.

Schematic only · physical contact positions unconfirmed. Original drawing · not to scale. Scroll sideways if needed.

SATA-IO external single-lane connector (historical draft assignment) — source-scoped contact map
Pin	Signal	What it does	Status
1	GND	Ground reference and return.	Single source Sources
2	A+	Control, detection or configuration connection; check the source and device.	Single source Sources
3	A-	Control, detection or configuration connection; check the source and device.	Single source Sources
4	GND	Ground reference and return.	Single source Sources
5	B-	Control, detection or configuration connection; check the source and device.	Single source Sources
6	B+	Control, detection or configuration connection; check the source and device.	Single source Sources
7	GND	Ground reference and return.	Single source Sources

Sources (2)

S743 · Serial ATA International Organization · Serial ATA Revision 3.0: Technical Integration WG Changes (037_SATA26_2009_02_27_Technical_Integration_WG_Changes.pdf)
Draft v0.108, Jan. 20, 2009, with review comments; NOT a final adopted specification · printed p.148 (PDF p.153), §6.5.1 external single-lane usage explicitly refers to Table 4; printed p.80 (PDF p.85), Table 4 signal segment
S744 · Advantech Co., Ltd. · ARK-3440 User Manual
Part No. 2006344001, Edition 2, April 2012 · printed p.10 (PDF p.22), §2.2.6 and Figure 2.8 eSATA connector numbered host face; no signal map supplied

eSATA host plug

View and evidence limits

Numbered external plug contacts; Figure 94 is the RA SMT plug, Figure 95 a distinct reversed-pinout implementation. No universal board-tail mirror is claimed.

P118 eSATA — **Agree**: ground on S1/S4/S7, A+/A- on S2/S3, B-/B+ on S5/S6 — A uses an explicitly identified historical SATA-IO draft plus an Advantech face drawing. B retrieved public **SATA 3.0 Gold, June 2009**, including host/device assignments and separate physical implementations. That fills A's missing final-edition evidence for the historical interface. Same standards issuer and related editions, not independent issuers; no current-edition compliance or powered-eSATA map is claimed.
eSATAp/USB combination power contacts and exact shell-to-board grounding are separate and unverified here.

Schematic only · physical contact positions unconfirmed. Original drawing · not to scale. Scroll sideways if needed.

eSATA host plug — source-scoped contact map
Pin	Signal	What it does	Status
S1	GND	Ground reference and return.	Single source Sources
S2	A+	Control, detection or configuration connection; check the source and device.	Single source Sources
S3	A-	Control, detection or configuration connection; check the source and device.	Single source Sources
S4	GND	Ground reference and return.	Single source Sources
S5	B-	Control, detection or configuration connection; check the source and device.	Single source Sources
S6	B+	Control, detection or configuration connection; check the source and device.	Single source Sources
S7	GND	Ground reference and return.	Single source Sources

Sources (1)

S745 · Serial ATA International Organization (SATA-IO) · Serial ATA Revision 3.0
Gold Revision, June 2, 2009 · p. 82, section 6.1.3.2, Table 3 Signal and Power SATA Plug and Nominal Mate Sequence; p. 69, Figure 17 SATA Cable / Connector Connection Diagram; p. 149 section 6.5.1 opposite host/device definitions; pp. 149-153, section 6.5.1; Figure 93 cable receptacle, Figure 94 RA SMT plug and Figure 95 reversed-pinout version

eSATA device plug

View and evidence limits

Numbered external plug contacts; Figure 94 is the RA SMT plug, Figure 95 a distinct reversed-pinout implementation. No universal board-tail mirror is claimed.

P118 eSATA — **Agree**: ground on S1/S4/S7, A+/A- on S2/S3, B-/B+ on S5/S6 — A uses an explicitly identified historical SATA-IO draft plus an Advantech face drawing. B retrieved public **SATA 3.0 Gold, June 2009**, including host/device assignments and separate physical implementations. That fills A's missing final-edition evidence for the historical interface. Same standards issuer and related editions, not independent issuers; no current-edition compliance or powered-eSATA map is claimed.
eSATAp/USB combination power contacts and exact shell-to-board grounding are separate and unverified here.

Schematic only · physical contact positions unconfirmed. Original drawing · not to scale. Scroll sideways if needed.

eSATA device plug — source-scoped contact map
Pin	Signal	What it does	Status
S1	GND	Ground reference and return.	Single source Sources
S2	A+	Control, detection or configuration connection; check the source and device.	Single source Sources
S3	A-	Control, detection or configuration connection; check the source and device.	Single source Sources
S4	GND	Ground reference and return.	Single source Sources
S5	B-	Control, detection or configuration connection; check the source and device.	Single source Sources
S6	B+	Control, detection or configuration connection; check the source and device.	Single source Sources
S7	GND	Ground reference and return.	Single source Sources

Sources (1)

S745 · Serial ATA International Organization (SATA-IO) · Serial ATA Revision 3.0
Gold Revision, June 2, 2009 · p. 82, section 6.1.3.2, Table 3 Signal and Power SATA Plug and Nominal Mate Sequence; p. 69, Figure 17 SATA Cable / Connector Connection Diagram; p. 149 section 6.5.1 opposite host/device definitions; pp. 149-153, section 6.5.1; Figure 93 cable receptacle, Figure 94 RA SMT plug and Figure 95 reversed-pinout version

Unknowns stay unknown.

Check the exact device manual before wiring or applying power.

Your next step

Use the detail without guessing past its limits.

Read the connector field note Recognition clues and practical checks.Work through a connection Keep exact equipment and cable requirements separate.

Source trail

Claims and sources

C805Esource checked

SATA-IO external single-lane connector (historical draft assignment): original contact normalization. Statuses distinguish comparison agreement, source limits and named-device wiring.

Serial ATA International Organization · Serial ATA Revision 3.0: Technical Integration WG Changes (037_SATA26_2009_02_27_Technical_Integration_WG_Changes.pdf) ↗
printed p.148 (PDF p.153), §6.5.1 external single-lane usage explicitly refers to Table 4; printed p.80 (PDF p.85), Table 4 signal segment · Source scope and unresolved evidence are preserved in the engineering variant.

Advantech Co., Ltd. · ARK-3440 User Manual ↗
printed p.10 (PDF p.22), §2.2.6 and Figure 2.8 eSATA connector numbered host face; no signal map supplied · Source scope and unresolved evidence are preserved in the engineering variant.

C805Fsource checked

eSATA host plug: original contact normalization. Statuses distinguish comparison agreement, source limits and named-device wiring.

Serial ATA International Organization (SATA-IO) · Serial ATA Revision 3.0 ↗
p. 119, section 6.2.4.5, Table 10 Signal and Power Internal Micro SATA Plug and Nominal Mate Sequence, including notes 4-6; p. 69, Figure 17 SATA Cable / Connector Connection Diagram; p. 149 section 6.5.1 opposite host/device definitions; p. 82, section 6.1.3.2, Table 3 Signal and Power SATA Plug and Nominal Mate Sequence; p. 83, Figure 30 Connector Pin and Feature Locations; pp. 131-132, Table 13 Slimline Device plug connector pin definition and Figure 76 Slimline Connector Pin and Feature Locations; pp. 149-153, section 6.5.1; Figure 93 cable receptacle, Figure 94 RA SMT plug and Figure 95 reversed-pinout version · Source scope and unresolved evidence are preserved in the engineering variant.

C805Gsource checked

eSATA device plug: original contact normalization. Statuses distinguish comparison agreement, source limits and named-device wiring.

3 source records support this profile. No independent engineering review or hardware validation is claimed.

Evidence behind this page

Scope first. Source second. Approval separate.

3 linked sources · 3 scoped claims · 0 sources with inspection/access flags.

Page scope: Original schematic; not to scale and not fabrication approval.

Assessment 2026-10-22 · earliest scheduled source review 2027-01-19. This is a recorded-date assessment, not a live source check. Page-level independent review is not established by this panel.

Inspect 3 source scopes, access limits and dates

S743 · Serial ATA Revision 3.0: Technical Integration WG Changes (037_SATA26_2009_02_27_Technical_Integration_WG_Changes.pdf)

Serial ATA International Organization · Unclassified publisher domain · inspected 2026-10-21 · due 2027-01-19

Within inspection window

Scoped support: Exact named pinout variant only; not capability or compatibility approval.

Not established / limitations: Source scope and unresolved evidence are preserved in the engineering variant.

Locator: printed p.148 (PDF p.153), §6.5.1 external single-lane usage explicitly refers to Table 4; printed p.80 (PDF p.85), Table 4 signal segment

S744 · ARK-3440 User Manual

Advantech Co., Ltd. · Unclassified publisher domain · inspected 2026-10-21 · due 2027-01-19

Within inspection window

Scoped support: Exact named pinout variant only; not capability or compatibility approval.

Not established / limitations: Source scope and unresolved evidence are preserved in the engineering variant.

Locator: printed p.10 (PDF p.22), §2.2.6 and Figure 2.8 eSATA connector numbered host face; no signal map supplied

S745 · Serial ATA Revision 3.0

Serial ATA International Organization (SATA-IO) · Unclassified publisher domain · inspected 2026-10-21 · due 2027-01-19

Within inspection window

Scoped support: Exact named pinout variant only; not capability or compatibility approval.

Not established / limitations: Source scope and unresolved evidence are preserved in the engineering variant.

Locator: p. 119, section 6.2.4.5, Table 10 Signal and Power Internal Micro SATA Plug and Nominal Mate Sequence, including notes 4-6; p. 69, Figure 17 SATA Cable / Connector Connection Diagram; p. 149 section 6.5.1 opposite host/device definitions; p. 82, section 6.1.3.2, Table 3 Signal and Power SATA Plug and Nominal Mate Sequence; p. 83, Figure 30 Connector Pin and Feature Locations; pp. 131-132, Table 13 Slimline Device plug connector pin definition and Figure 76 Slimline Connector Pin and Feature Locations; pp. 149-153, section 6.5.1; Figure 93 cable receptacle, Figure 94 RA SMT plug and Figure 95 reversed-pinout version

Trace 3 claims to their source records

C805E · P118

SATA-IO external single-lane connector (historical draft assignment): original contact normalization. Statuses distinguish comparison agreement, source limits and named-device wiring.

Claim scope: Pinout variant only; see comparison and per-contact status. Not fabrication approval.

Source links: S743 · S744 · Evidence trail → (private workspace)

C805F · P118

eSATA host plug: original contact normalization. Statuses distinguish comparison agreement, source limits and named-device wiring.

Claim scope: Pinout variant only; see comparison and per-contact status. Not fabrication approval.

Source links: S745 · Evidence trail → (private workspace)

C805G · P118

eSATA device plug: original contact normalization. Statuses distinguish comparison agreement, source limits and named-device wiring.

Claim scope: Pinout variant only; see comparison and per-contact status. Not fabrication approval.

Source links: S745 · Evidence trail → (private workspace)

Prepare this page for review →Read the evidence method →

Recorded evidence only. An inspection date, publisher label, source link or generated packet is not independent technical review, hardware testing, fabrication approval or a compatibility verdict.